This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.

https://web.iitd.ac.in/~mamidala/HTMLobj-161/March04.pdf

Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review

The RF noise in 0.18-/spl mu/m CMOS technology has been measured and modeled. In contrast to some other groups, we find only a moderate enhancement of the drain current noise for short-channel MOSFETs. The gate current noise on the other hand is more significantly enhanced, which is explained by the effects of the gate resistance. The experimental results are modeled with a nonquasi-static RF model, based on channel segmentation, which is capable of predicting both drain and gate current noise accurately. Experimental evidence is shown for two additional noise mechanisms: 1) avalanche noise associated with the avalanche current from drain to bulk and 2) shot noise in the direct-tunneling gate leakage current. Additionally, we show low-frequency noise measurements, which strongly point toward an explanation of the 1/f noise based on carrier trapping, not only in n-channel MOSFETs, but also in p-channel MOSFETs.

/pdf/noise-modeling-for-rf-cmos-circuit-simulation-16f065ze5x.pdf

Noise modeling for RF CMOS circuit simulation

The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.

Production and propagation of single-event transients in high-speed digital logic ICs

An overview is given of recent theoretical concepts and experimental findings with respect to the flicker or 1/ f noise in advanced silicon MOSFETs. First, a summary will be given of the theoretical models which to date are being considered for modeling of the flicker noise phenomenon. These will be confronted with experimental evidence, from which the likely validity range of the different models and their possible limitations follow. Next, attention will be paid to the impact of technology scaling to submicron dimensions on the 1/ f noise. Finally, the effect of specific advanced processing steps, typical for submicron CMOS technology will be highlighted and guidelines for low-noise processing will be formulated.

On the flicker noise in submicron silicon MOSFETs

Low-cost manufacturing, high yields and seamless on-chip integration with electronics are often touted as the guaranteed benefits of silicon photonics, but is this really the case? Michael Hochberg and colleagues explain that the situation is much more complex in reality.

Myths and rumours of silicon photonics

A new non-quasi-static (NQS) MOSFET model, which is applicable for both large-signal transient and small-signal ac analysis, has been developed. It employs a physical relaxation time approach to take care of the finite channel charging time to reach equilibrium and the effect of instantaneous channel charge re-distribution. The NQS model is formulated independently from the dc I-V and the charge-capacitor model, thus can be easily applied to any existing simulators. The model has been implemented in the newly released BSIM3 version 3, and comparison has been made among this model, common quasi-static (QS) SPICE models and PISCES two-dimensional (2-D) numerical device simulator. While predicting accurate NQS behavior, the time penalty for using the new model is only about 20-30% more than the common QS models. It is much less than the time required by other NQS models reported. Limitations and compromises between simplicity, efficiency and accuracy are also discussed.

/pdf/a-robust-and-physical-bsim3-non-quasi-static-transient-and-3t4u044bjq.pdf

A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

The threshold voltage, V/sub th/, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V/sub th/ roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, /spl Delta/V/sub th/ is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V/sub th/ design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V/sub th/ design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained. >

Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E/sub m/). Experimental results using SOI MOSFET's with body contacts indicate that E/sub m/ is just a weak function of thin-film SOI thickness (T/sub si/ and that E/sub m/ can be significantly lower than in a bulk device with drain junction depth (X/sub j/) comparable to SOI's T/sub si/. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I/sub G/) of studying E/sub m/ in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought. >

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Floating-body partially depleted (PD) SOI MOSFET's exhibit excess low-frequency noise. For the first time, the origin of the excess noise is identified to be the shot noise associated with impact ionization current and body-source diode current. The shot noise, normally negligible as compared with flicker noise, is amplified in the device through the floating-body effect (FEE). A physically-based noise model is proposed which predicts that the excess low-frequency noise shows a Lorentzian-like spectrum as verified by experimental data. The physical explanation is further supported by the coincidence of the characteristic frequency in noise spectrum and AC output impedance of the device.

Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFET's

The mobility crossover phenomenon observed in NH/sub 3/-nitrided N-MOSFET's has been interpreted by the reduced acceptor-type interface states which are located near and above the conduction band edge. However. A direct confirmation of such a hypothesis is not available from the conventional electrical measurement techniques. In this work, for the first time, we used both 1/f noise and random telegraph signal (RTS) measurements which are capable of probing those oxide traps near and above Si conduction band of energy, to study the modification of interface traps induced by N/sub 2/O nitridation. The 1/f noise measurement results confirm that thermal nitridation decreases the near-interface oxide trap density at the higher energy levels, as a result, trapping of the mobile electrons is decreased. The RTS measurement further suggests that thermal nitridation moves the oxide traps farther away from the Si-SiO/sub 2/ interface and thus suppresses the Coulombic scattering of mobile electrons by the trapped charges. Both nitridation-induced interfacial modifications result in enhanced high-field mobility of nitrided-oxide devices over the standard MOS devices. >

P.K. Ko

Papers

A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

Threshold voltage model for deep-submicrometer fully depleted SOI MOSFET's

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Shot-noise-induced excess low-frequency noise in floating-body partially depleted SOI MOSFET's

New insight into high-field mobility enhancement of nitrided-oxide N-MOSFET's based on noise measurement