Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 mu V at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 mu V at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW. >

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Design techniques for high-speed, high-resolution comparators

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process. >

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

A pipelined, 5-Msample/s, 9-b analog-to-digital converter with digital correction has been designed and fabricated in 3-/spl mu/m CMOS technology. It requires 8500 mil/SUP 2/, consumes 180 mW, and has an input capacitance of 3 pF. A fully differential architecture is used; only a two-phase nonoverlapping clock is required, and an on-chip sample-and-hold amplifier is included.

https://www.ee.columbia.edu/~kinget/EE6312_S04/project/refs/lewis_pipelined_ad_jssc_dec_1987.pdf

A pipelined 5-Msample/s 9-bit analog-to-digital converter

A self-calibrating analog-to-digital converter using binary weighted capacitors and resistor strings is described. Linearity errors are corrected by a simple digital algorithm. A folded cascode CMOS comparator resolves 30 /spl mu/V in 3 /spl mu/s. An experimental converter fabricated using a 6-/spl mu/m-gate CMOS process demonstrates 15-bit resolution and linearity at a 12-kHz sampling rate.

A self-calibrating 15 bit CMOS A/D converter

A resolution-rate scalable ADC for micro-sensor networks is described. Based on the successive approximation register (SAR) architecture, this ADC has two resolution modes: 12 bit and 8 bit, and its sampling rate is scalable, at a constant figure-of-merit, from 0-100 kS/s and 0-200 kS/s, respectively. At the highest performance point (i.e., 12 bit, 100 kS/s), the entire ADC (including digital, analog, and reference power) consumes 25 muW from a 1-V supply. The ADC's CMRR is enhanced by common-mode independent sampling and passive auto-zero reference generation. The efficiency of the comparator is improved by an analog offset calibrating latch, and the preamplifier settling time is relaxed by self-timing the bit-decisions. Prototyped in a 0.18-mum, 5M2P CMOS process, the ADC, at 12 bit, 100 kS/s, achieves a Nyquist SNDR of 65 dB (10.55 ENOB) and an SFDR of 71 dB. Its INL and DNL are 0.68 LSB and 0.66 LSB, respectively

An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes

Improved computer-aided analog-to-digital converter (ADC) characterization methods based on the code density test and spectral analysis using the fast Fourier transform are described. The code density test produces a histogram of the digital output codes of an ADC sampling a known input. The code density can be interpreted to compute the differential and integral nonlinearities, gain error, offset error, and internal noise. Conversion-rate and frequency-dependent behavior can also be measured.

Full-speed testing of A/D converters

A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

A 10-bit 5-Msample/s CMOS two-step flash ADC

A 10-bit, 5-Msample/s, two-step flash A/D (analog-to-digital) converter fabricated in a 1.6- mu m CMOS process is described. With minimal capacitor-matching requirements and comparator offset-voltage cancellation, the architecture is monotonic. To minimize charge-injection errors, the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000 and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54k square mils. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

J. Doernberg

Papers

Full-speed testing of A/D converters

A 10-bit 5-Msample/s CMOS two-step flash ADC

A 10-bit 5 Msample/sec CMOS 2-step flash ADC