Current medical imaging technologies allow visualization of tissue anatomy in the human body at resolutions ranging from 100 micrometers to 1 millimeter. These technologies are generally not sensitive enough to detect early-stage tissue abnormalities associated with diseases such as cancer and atherosclerosis, which require micrometer-scale resolution. Here, optical coherence tomography was adapted to allow high-speed visualization of tissue in a living animal with a catheter-endoscope 1 millimeter in diameter. This method, referred to as "optical biopsy," was used to obtain cross-sectional images of the rabbit gastrointestinal and respiratory tracts at 10-micrometer resolution.

In Vivo Endoscopic Optical Biopsy with Optical Coherence Tomography

Reliability challenges in 3D IC packaging technology

Purpose – The purpose of this paper is to focus on through‐silicon via (TSV), with a new concept that every chip or interposer could have two surfaces with circuits. Emphasis is placed on the 3D IC integration, especially the interposer (both active and passive) technologies and their roadmaps. The origin of 3D integration is also briefly presented.Design/methodology/approach – This design addresses the electronic packaging of 3D IC integration with a passive TSV interposer for high‐power, high‐performance, high pin‐count, ultra fine‐pitch, small real‐estate, and low‐cost applications. To achieve this, the design uses chip‐to‐chip interconnections through a passive TSV interposer in a 3D IC integration system‐in‐package (SiP) format with excellent thermal management.Findings – A generic, low‐cost and thermal‐enhanced 3D IC integration SiP with a passive interposer has been proposed for high‐performance applications. Also, the origin of 3D integration and the overview and outlook of 3D Si integration and 3...

Overview and outlook of through‐silicon via (TSV) and 3D integrations

Continual scaling of on-chip wiring structures has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, 3-D integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirement. Among others, thermomechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. This paper examines the effects of thermally induced stresses on the interfacial reliability of TSV structures. First, 3-D distribution of the thermal stress near the TSV and the wafer surface is analyzed. Using a linear superposition method, a semianalytic solution is developed for a simplified structure consisting of a single TSV embedded in a silicon (Si) wafer. The solution is verified for relatively thick wafers by comparing to numerical results from finite element analysis (FEA). The stress analysis suggests interfacial delamination as a potential failure mechanism for the TSV structure. An analytical solution is then obtained for the steady-state energy release rate as the upper bound for the interfacial fracture driving force, while the effect of crack length is evaluated numerically by FEA. With these results, the effects of the TSV dimensions (e.g., via diameter and wafer thickness) on the interfacial reliability are elucidated. Furthermore, the effects of via material properties and dielectric buffer layers are discussed.

/pdf/impact-of-near-surface-thermal-stresses-on-interfacial-37n8923q10.pdf

Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects

The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control phys ...

/pdf/integrating-mems-and-ics-3tx6wanytd.pdf

Integrating MEMS and ICs

Most TSVs are filled with copper; siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5 times 10-6/degC) is a few times higher than that of silicon (~2.5 times10-6/degC). Thus, when the copper filled through silicon via (TSV) is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this paper, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10 times 10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for 1) making a decision if underfill is necessary for the reliability of microbumps and 2) selecting underfill materials to minimize the stresses and strains in the microbumps.

Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5x10-6/degC) is a few times higher than that of silicon (~2.5x10-6/degC). Thus, when the copper filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this study, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10x10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for (1) making a decision if underfills are necessary for the reliability of microbumps, and (2) selecting underfill materials to minimize the stresses and strains in the microbumps.

Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

Three dimensional system-in-package (3D SiP) based on silicon carriers or interposer is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through silicon via (TSV). The development of 3D SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to poor RF performance. In this paper, a coaxial TSV structure in silicon carrier is presented for high frequency applications. The coaxial TSV is able to suppress undesirable substrate loss as well as provide good impedance matching. Electrical modeling of coaxial TSV structure was carried out to obtain the required geometries for impedance matching. Three different types of test vehicles were fabricated; Cu-plug TSV in both low (~10 Omega-cm) and high resistivity (~4000 Omega-cm) silicon substrate, and coaxial TSV in low resistivity silicon substrate. The S-parameters of the via structure of the test vehicles were measured from 100 MHz to 10 GHz. The measured results show that the coaxial TSV structure is able to suppress silicon substrate loss and provide good RF performance compared to Cu-plug TSV structure.

High RF performance TSV silicon carrier for high frequency application

The primary trend in electronics industry is product miniaturization Both design and manufacturing engineers are looking for ways to make products lighter, smaller, less expensive, and at the same time faster, more powerful, reliable, user-friendly, and functional A partial list of today's "shrinking" products would include cellular phones, personal and sub-notebook computers, pagers, PCMCIA cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components With silicon chips continue integrating more functionality as per Moore's law, the packaging is challenged to integrate and shrink Chips first or embedded chip packaging is a revolutionary way to overcome these recent packaging integration challenges Packaging researchers have worked on embedded packaging and developed newer way of embedding the chip The PBGA replaced the lead frame based peripheral array packages, in which the die is electrically connected to circuit board (PCB) substrate by wire bonding or flip chip technology, before covering with molding compound Embedded Wafer level packaging takes the next step, eliminating the PCB, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection This paper deals with the development embedding multiple dies at wafer level A detailed mechanical and structural analysis of the package in terms of the die thickness, wafer size and warpage is presented The package format is suitable for stacking multiple die in 3D format and 2D format The paper also deals with characterization of the materials and the process integration of the multidie wafer level packaging Initial reliability results of the package are also presented

Design and development of a multi-die embedded micro wafer level package

In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO2/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic compound (IMC) phases of In-Cu and In-Au IMCs after bonding below 180degC and annealing at 100~120degC. The IMC in the joints were characterized in terms of the micro structure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, Cu11ln9, Cu2In, eta-Cu6Sn5, and Auln2, was successfully made at 120degC followed by annealing at 100degC in Type 3, and at 160degC with annealing for lOhrs or at 180degC without annealing for Type 1, which was confirmed by DSC measurements and explained through thermodynamic calculations.

J.H. Lau

Papers

Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

High RF performance TSV silicon carrier for high frequency application

Design and development of a multi-die embedded micro wafer level package

Development of low temperature bonding using in-based solders