scispace - formally typeset
X

Xiaowu Zhang

Researcher at Agency for Science, Technology and Research

Publications -  203
Citations -  3160

Xiaowu Zhang is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Flip chip & Die (integrated circuit). The author has an hindex of 25, co-authored 198 publications receiving 2770 citations. Previous affiliations of Xiaowu Zhang include Singapore Science Park & Hong Kong University of Science and Technology.

Papers
More filters
Journal ArticleDOI

Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps

TL;DR: In this article, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter).
Proceedings ArticleDOI

Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

TL;DR: In this article, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter).
Journal ArticleDOI

The study of mechanical properties of Sn–Ag–Cu lead-free solders with different Ag contents and Ni doping under different strain rates and temperatures

TL;DR: In this paper, the effect of Ag content and Ni doping on the microstructures and mechanical properties of solders was investigated for each solder using stain rates of 10−5 ǫ s−1, 10−4 ǒ s− 1, 10 −3 ǔ s− 2, 10¼ s− 3 and 10−1 Ǫ s− 4 ǎ s− 5. The results showed that the elastic modulus, yield stress and ultimate tensile strength increase with increasing strain rate and Ag content, but decrease with increasing temperature
Journal ArticleDOI

High-Density 3D-Boron Nitride and 3D-Graphene for High-Performance Nano-Thermal Interface Material.

TL;DR: Comparative studies to state-of-the-art materials and other materials currently under research for heat dissipation revealed 3D-foam's improved performance (20-30% improved cooling, temperature decrease by ΔT of 44-24 °C).
Proceedings ArticleDOI

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

TL;DR: In this article, the TSV interposer was used to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate.