T
Tai Chong Chai
Researcher at Agency for Science, Technology and Research
Publications - 73
Citations - 1257
Tai Chong Chai is an academic researcher from Agency for Science, Technology and Research. The author has contributed to research in topics: Flip chip & Die (integrated circuit). The author has an hindex of 15, co-authored 71 publications receiving 1122 citations. Previous affiliations of Tai Chong Chai include Singapore Science Park.
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Journal ArticleDOI
Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
TL;DR: In this article, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter).
Proceedings ArticleDOI
Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps
TL;DR: In this article, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter).
Proceedings ArticleDOI
Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package
Xiaowu Zhang,Tai Chong Chai,John H. Lau,C. S. Selvanayagam,Kalyan Biswas,Shiguo Liu,Damaruganath Pinjala,Gongyue Tang,Yue Ying Ong,Srinivasa Rao Vempati,Eva Wai,Hongyu Li,Ebin Liao,Nagarajan Ranganathan,V. Kripesh,Jiangyan Sun,John Doricko,C. J. Vath +17 more
TL;DR: In this article, the TSV interposer was used to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate.
Journal ArticleDOI
Electromigration performance of Through Silicon Via (TSV) – A modeling approach
TL;DR: The electromigration (EM) performance of Through Silicon Via (TSV) in silicon interposer application are studied using Finite Element (FE) modeling and it is found that thermo-mechanical stress is the dominant contribution factor to EM performance in TSV.
Journal ArticleDOI
Development of Large Die Fine-Pitch Cu/Low- $k$ FCBGA Package With Through Silicon via (TSV) Interposer
Tai Chong Chai,Xiaowu Zhang,John H. Lau,C. S. Selvanayagam,Pinjala Damaruganath,Yen Yi Germaine Hoe,Yue Ying Ong,Vempati Srinivasa Rao,Eva Wai,Hong Yu Li,Ebin Liao,Nagarajan Ranganathan,Kripesh Vaidyanathan,Shiguo Liu,Jiangyan Sun,M Ravi,C. J. Vath,Y Tsutsumi +17 more
TL;DR: In this paper, the TSV interposer was used for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package.