Predictions and measurements of the effect of biaxial strain on the properties of epitaxial ferroelectric thin films and superlattices are reviewed. Results for single-layer ferroelectric films of biaxially strained SrTiO3, BaTiO3, and PbTiO3 as well as PbTiO3/SrTiO3 and BaTiO3/SrTiO3 superlattices are described. Theoretical ap- proaches, including first principles, thermodynamic analysis, and phase-field models, are applied to these biaxially strained materials, the assumptions and limitations of each technique are explained, and the predictions are compared. Measurements of the effect of biax- ial strain on the paraelectric-to-ferroelectric transition temperature (TC) are shown, demonstrating the ability of percent-level strains to shift TC by hundreds of degrees in agreement with the predic- tions that predated such experiments. Along the way, important ex- perimental techniques for characterizing the properties of strained ferroelectric thin films and superlattices, as well as appropriate sub- strates on which to grow them, are mentioned.

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Strain Tuning of Ferroelectric Thin Films

This article reviews the history and current progress in high-mobility strained Si, SiGe, and Ge channel metal-oxide-semiconductor field-effect transistors (MOSFETs). We start by providing a chronological overview of important milestones and discoveries that have allowed heterostructures grown on Si substrates to transition from purely academic research in the 1980’s and 1990’s to the commercial development that is taking place today. We next provide a topical review of the various types of strain-engineered MOSFETs that can be integrated onto relaxed Si1−xGex, including surface-channel strained Si n- and p-MOSFETs, as well as double-heterostructure MOSFETs which combine a strained Si surface channel with a Ge-rich buried channel. In all cases, we will focus on the connections between layer structure, band structure, and MOS mobility characteristics. Although the surface and starting substrate are composed of pure Si, the use of strained Si still creates new challenges, and we shall also review the litera...

Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors

Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

Frontiers of silicon-on-insulator

Silicon-based heterostructures have come a long way from the discovery of strain as a new and essential parameter for band structure engineering to the present state of electron and hole mobilities, which surpass those achieved in the traditional material combination by more than an order of magnitude and are rapidly approaching the best III - V heteromaterials. It is the purpose of this article to report on the most recent developments, and the performance level achieved to date in this material system, in a concise and critical manner. The first part of this review is concerned with the structural and electronic properties of the lattice-mismatched Si/SiGe heterostructure. Emphases are put on the effects of strain both on the band structure and on the band offsets, as well as on means to actually control the strain in a stack of heteroepitaxial layers. The second part is dedicated to the transport properties of low-dimensional carrier systems in Si/SiGe and Ge/SiGe heterostructures. The prospects and limitations of the different layer concepts are discussed in terms of scattering mechanisms and experimental results. This part also reviews the most recent magneto-transport experiments on quantum wires and quantum point contacts, which became possible by the enhanced mean free paths in these materials. The third part covers the device aspects of these high-mobility materials, which is of special interest, because silicon-based heterostructures can significantly enhance the performance level of contemporary Si devices without sacrificing the essential compatibility with standard Si technologies. The recent achievements in this application-driven research field, but also the foreseeable problems and limitations, are discussed, and an assessment of the possible role of such heterodevices in future microelectronic circuits is given.

http://iopscience.iop.org/article/10.1088/0268-1242/12/12/001/pdf

High-mobility Si and Ge structures

Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.

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Theory of ballistic nanotransistors

Enhanced performance is demonstrated in n-type metal-oxide-semiconductor field-effect transistors with channel regions formed by pseudomorphic growth of strained Si on relaxed Si/sub 1/spl minus/x/Ge/sub x/ Standard MOS fabrication techniques were utilized, including thermal oxidation of the strained Si Surface channel devices show low-field mobility enhancements of 80% at room temperature and 12% at 10 K, when compared to control devices fabricated in Czochralski Si Similar enhancements are observed in the device transconductance In addition, buried channel devices show peak room temperature mobilities about three times that of control devices >

Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors

We report the first measurements on deep submicron strained-Si n-MOSFETs. In spite of the high channel doping and vertical effective fields, electron mobility is enhanced by /spl sim/75% compared to typical MOSFET mobilities. The extrinsic transconductance is increased by /spl sim/45% for channel lengths of 0.1 /spl mu/m, when AC measurements are used to reduce self-heating effects. The improved transconductance demonstrates the use of strain-induced enhancements in both mobility and high-field transport to increase the average electron velocity, while maintaining the channel doping required to suppress short channel effects.

Transconductance enhancement in deep submicron strained Si n-MOSFETs

The strain dependence of the hole mobility in surface-channel p-MOSFETs employing pseudomorphic, strained-Si layers is reported for the first time. The hole mobility enhancement is observed to increase roughly linearly with the strain as the Ge content in the relaxed Si/sub 1-x/Ge/sub x/ buffer layer increases. When compared to the device with x=0.1, the devices with x=0.22 and 0.29 exhibit hole mobility enhancement factors of 1.4 and 1.8, respectively. In spite of the high fixed charge in our gate oxides, the device with Ge content x=0.29 still exhibits a mobility 1.3 times that of bulk Si MOSFETs with state-of-the-art oxides. The first measurements of the transconductance enhancements in submicron strained-Si p-MOSFETs are also reported.

Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs

Si/Si/sub 1-x/Ge/sub x/ heterojunction transistors (HBTs) fabricated by a chemical vapor deposition (CVD) technique are reported. A rapid thermal CVD limited-reaction processing (LRP) technique was used for the in situ growth of all three device layers, including a 20-mm Si/sub 1-x/Ge/sub x/ layer in the base. The highest current gains observed ( beta =400) were for a Si/Si/sub 1-x/Ge/sub x/ HBT with a base doping of 7*10/sup 18/ cm/sup -3/ near the junction and a shallow arsenic implant to form ohmic contacts and increase current gain. Ideal base currents were observed for over six decades of current and the collector current remained ideal for nearly nine current decades starting at 1 pA. The bandgap difference between a p-type Si layer doped to 5*10/sup 17/ cm/sup -3/ and the Si/sub 1-x/Ge/sub x/(x=0.31) base measured 0.27 eV. This value was deduced from the measurements of the temperature dependence of the base current and is in good agreement with published calculations for strained Si/sub 1-x/Ge/sub x/ layers on Si. >

Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors produced by limited reaction processing

Si/Si/sub 1-x/Ge/sub x//Si N-p-N heterojunction bipolar transistors (HBTs) produced by a chemical vapor deposition technique, limited-reaction processing, were analyzed using electrical measurements to determine properties of strained Si/sub 1-x/Ge/sub x/. The band discontinuities between Si and strained Si/sub 1-x/Ge/sub x/ were found by measuring the collector and base currents as a function of temperature. The electron diffusion coefficient in p-type Si/sub 1-x/Ge/sub x/ was extracted by measuring the change in collector current with Si/sub 1-x/Ge/sub x/ base width. The electron diffusion coefficient perpendicular to the heterointerface in the strained Si/sub 1-x/Ge/sub x/ layers studied here is smaller than that in Si doped to the same level. The reverse leakage currents at the base-emitter junction of the HBTs are smaller than the leakage at the collector-base junction, but in Si control transistors the situation is reversed. The high leakage currents at the collector-base junction in the HBTs are believed to result from the preferred accumulation of misfit dislocations at the strained interface closest to the substrate. >

J. L. Hoyt

Papers

Electron mobility enhancement in strained-Si n-type metal-oxide-semiconductor field-effect transistors

Transconductance enhancement in deep submicron strained Si n-MOSFETs

Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs

Si/Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors produced by limited reaction processing

Bandgap and transport properties of Si/sub 1-x/Ge/sub x/ by analysis of nearly ideal Si/Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors