For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication

Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

InP-Based Transistor Fabrication

Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.

Tri-gate field-effect transistors formed by aspect ratio trapping

We report the use of highly ordered, dense, and regular arrays of in-plane GaAs nanowires as building blocks to produce antiphase-domain-free GaAs thin films on exact (001) silicon. High quality GaAs nanowires were grown on V-grooved Si (001) substrates using the selective aspect ratio trapping concept. The 4.1% lattice mismatch has been accommodated by the initial GaAs, a few nanometer-thick with high density stacking faults. The bulk of the GaAs wires exhibited smooth facets and a low defect density. An unusual defect trapping mechanism by a “tiara”-like structure formed by Si undercuts was discovered. As a result, we were able to grow large-area antiphase-domain-free GaAs thin films out of the nanowires without using SiO2 sidewalls for defect termination. Analysis from XRD ω-rocking curves yielded full-width-at-half-maximum values of 238 and 154 arc sec from 900 to 2000 nm GaAs thin films, respectively, indicating high crystalline quality. The growth scheme in this work offers a promising path towards ...

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Growing antiphase-domain-free GaAs thin films out of highly ordered planar nanowire arrays on exact (001) silicon

Metal-organic chemical vapor deposition growth of GaAs on Si was studied using the selective aspect ratio trapping method. Vertical propagation of threading dislocations generated at the GaAs∕Si interface was suppressed within an initial thin GaAs layer inside SiO2 trenches with aspect ratio >1, leading to defect-free GaAs regions up to 300nm in width. Cross-sectional and plan-view transmission electron microscopies were used to characterize the defect reduction. Material quality was confirmed by room temperature photoluminescence measurements. This approach shows great promise for the fabrication of optoelectronic integrated circuits on Si substrates.

Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping

High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al2O3 as the gate oxide. The 10 μm gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of ∼500 cm2/Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.

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Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique

High quality, low defect GaAs virtual substrates on Si, produced by the aspect ratio trapping growth technique, have been used for the fabrication of n+GaAs/n+InGaAs/p+GaAs Esaki diodes. All epitaxial layers were grown by reduced-pressure chemical vapor deposition/metalorganic chemical vapor deposition , instead of the molecular beam epitaxy technique commonly used for most high performance Esaki diodes. Four Esaki diode structures were fabricated and measured, with current densities up to 1 kA/cm2. Peak-to-valley current ratios up to 56 have been achieved, which is greater than twice that of the best GaAs Esaki diodes previously reported.

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Record PVCR GaAs-based tunnel diodes fabricated on Si substrates using aspect ratio trapping

Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping

Recently much effort has been made in characterizing and realizing tunneling field effect transistors (TFET). Fundamental to the operation of such devices is the direct band-to-band tunneling of carriers from the n++ source to the p++ drain, which is the same current transport mechanism of Esaki Tunnel Diodes (ETD). Therefore, ETDs are an effective way to understand the potential of TFETs for high speed, low power applications. Recently, Rommel, et al. [1] reported on record breaking GaAs/InGaAs ETDs fabricated on Si substrates, with additional analysis by Pawlik, et al. [2]. However, these studies have been performed on large size devices with junction areas in excess of 5 μm2. Few studies of sub-micron ETDs have been performed [3], which is critical for integration of TFETs into modern VLSI/UVLSI circuits. This abstract reports on the fabrication and characterization of sub-micron GaAs/InGaAs ETDs on a Si substrate with junction areas below 0.1 μm2.

J. Li

Papers

Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping

Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique

Record PVCR GaAs-based tunnel diodes fabricated on Si substrates using aspect ratio trapping

Growth and characterization of GaAs layers on polished Ge/Si by selective aspect ratio trapping

Sub-micron Esaki Tunnel Diode fabrication and characterization