The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

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Power distribution networks for system-on-package: status and challenges

As the speed of signal through an interconnection increases toward the multigigabit ranges, the effects of lossy transmission lines on the signal quality of printed circuit boards becomes a critical issue. To evaluate the eye diagram and thus the signal integrity in the modern digital systems, this paper proposes a fast methodology that employs only two anti-polarity one-bit data patterns instead of the pseudo-random bit sequence as input sources to simulate the worst-case eye diagram. Analytic expressions are derived for the impulse response of the lossy transmission lines due to the skin-effect loss, while the Kramers-Kronig relations are employed to deal with the noncausal problem related to the dielectric loss. Two design graphs that can be used to rapidly predict the eye diagram characteristics versus the conductive and dielectric losses are then constructed and based on which, the maximally usable length of transmission lines under a certain signal specification can be easily acquired. At last, the time-domain simulations and experiments are implemented to verify the exactitude of proposed concept.

Fast Methodology for Determining Eye Diagram Characteristics of Lossy Transmission Lines

Compliant free-standing structures can be used as chip-to-substrate interconnects. Such ldquocompliant interconnectsrdquo are a potential solution to the requirements that will be imposed on chip-to-substrate interconnects over the next decade. However, cost of implementation and electrical performance limit compliant interconnects. In our previous work, we have proposed a new compliant interconnect technology called FlexConnect to address these concerns with compliant interconnects. An innovative cost-effective MEMS-based fabrication process is used to fabricate these compliant interconnects. Sequential lithography and electroplating processes with up to two masking steps are utilized. Utilizing the proposed fabrication process, in this paper, FlexConnects are realized at a 100-mum pitch. High-frequency modeling of the electrical parasitics of the interconnect is performed. Through finite-element-based models, the advantage of using multiple electrical paths as part of the interconnect design is shown from a thermomechanical reliability perspective. Finally, taking advantage of the MEMS-based photolithographic fabrication process, a heterogeneous combination of FlexConnects and column interconnects is proposed. This approach is shown to be an additional avenue to attain improved electrical performance without compromising mechanical performance.

Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect

Noise suppression and isolation in mixed-signal systems using alternating impedance electromagnetic bandgap (ai-ebg) structure

According to the latest ITRS roadmap, the pitch of area array packages is expected to decrease to 100 /spl mu/m by 2009. Simultaneously, the electrical performance of these interconnections needs to be improved to support data rates in excess of 10 Gbps, while guaranteeing thermomechanical reliability and lowering the cost. These requirements are challenging, thus, needing innovative interconnection designs and technologies. This paper describes the development of three interconnection schemes for wafer-level packages (WLPs) at 100-/spl mu/m pitch, involving rigid, compliant, and semicompliant interconnection technologies, extending the state of the art in each. Extensive electrical and mechanical modeling was carried out to optimize the geometry of the interconnections with respect to electrical performance and thermomechanical reliability. It was found that the requirements of electrical performance often conflict with those of thermomechanical reliability and the final "optimum" design is a tradeoff between the two. For the three interconnection schemes proposed, it was found that the electrical requirements can be met fairly well but acceptable mechanical reliability may require organic boards with a coefficient of thermal expansion of 10 ppm/K or lower.

Next generation of 100-/spl mu/m-pitch wafer-level packaging and assembly for systems-on-package

This paper discusses the design of a wafer level package on board for 5GHz data transmission. The design is based on the 2005 node of the International Technology Roadmap on Semiconductors (ITRS) that predicts a clock frequency of 5GHz, power of 170W and an operating voltage of 0.9V for high-end microprocessors. The goal of this paper is to demonstrate the ability to support global interconnections on the board at a speed comparable to the clock frequency and supply adequate power to the chip. This requires careful design of the topology of the interconnections, control of the eddy current losses in Silicon, control of the conductor and dielectric losses in the board and design of the transition between the chip and the board. The electrical design process is discussed in detail using a test vehicle, in this paper. The test vehicle consists of Co-planar waveguide (CPW) lines on high resistivity Silicon Substrate connected to CPW lines on low k, low loss board. The transition between the chip and board is completed through solder bumps with 50 /spl mu/m diameter and 100 /spl mu/m pitch. Both the Silicon and Board transmission lines have been characterized using TDR measurements. In addition, the inductance of the solder bumps have been extracted. Using synthesized models extracted from measurements, the eye diagrams for 5GHz data transmission has been simulated to show the importance of losses for 1mm long Silicon lines connected to 5cm long board lines through low inductance solder bumps. In addition, the effect of underfill and curing on signal propagation have been quantified.

http://ieeexplore.ieee.org/iel5/8973/28473/01271507.pdf

Electrical design of wafer level package on board for gigabit data transmission

This paper discusses the effect of wafer level packaging, silicon substrate, and board material on gigabit data transmission. A test vehicle consisting of a co-planar silicon transmission line, two board transmission lines and wafer level packaging was used for evaluation. A silicon substrate with 100 /spl Omega/-cm resistivity was compared with a silicon substrate with 2000 /spl Omega/-cm resistivity to investigate the effect of silicon substrate on gigabit data transmission. For board transmission lines, six board materials such as Ciba thin film, Vialux from Dupont, FR4, Hitachi MCL-LX67, Nelco N4000-12, and APPE were compared to investigate the effect of board material. For wafer-level packaging, solder bumps with 50 /spl mu/m diameter and 100 /spl mu/m pitch were used, and the effect of parasitic capacitance in the solder bumps on gigabit data transmission was investigated. For the accurate simulation of the test vehicle in the time domain, a TDR characterization method and non-physical RLGC models for lossy transmission lines were used to characterize board and silicon transmission lines. This paper shows that better signal integrity in the test vehicle cannot be achieved only by using lower loss material, but also requires low parasitic capacitance for gigabit data transmission.

J. Mao

Papers

Electrical design of wafer level package on board for gigabit data transmission

Effect of wafer level packaging, silicon substrate and board material on gigabit board-silicon-board data transmission