S
Suna Choi
Researcher at Georgia Institute of Technology
Publications - 4
Citations - 33
Suna Choi is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Flip chip & Printed circuit board. The author has an hindex of 4, co-authored 4 publications receiving 32 citations.
Papers
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Proceedings ArticleDOI
Electrical design of wafer level package on board for gigabit data transmission
Woopoung Kim,R. Madhavan,J. Mao,Jinwoo Choi,Suna Choi,D. Ravi,V. Sundaram,S. Sankararaman,Preeti Gupta,Z. Zhang,G. Lo,Madhavan Swaminathan,Rao Tummala,Suresh K. Sitaraman,C.P. Wong,M. Iyer,Mihai Rotaru,Andrew A. O. Tay +17 more
TL;DR: In this article, the design of a wafer level package on board for 5GHz data transmission has been discussed based on the 2005 node of the International Technology Roadmap on Semiconductors (ITRS).
Proceedings ArticleDOI
Electromagnetic modelling of switching noise in on-chip power distribution networks
TL;DR: In this article, the effect of substrate loss on the propagation of on-chip switching noise has been investigated using finite difference time domain (FDTD) technique, and the waveform and propagation pattern of the noise are captured using RLCG elements.
Proceedings ArticleDOI
Effect of wafer level packaging, silicon substrate and board material on gigabit board-silicon-board data transmission
Woopoung Kim,R. Madhavan,J. Mao,Jae Young Choi,Suna Choi,D. Ravi,V. Sundaram,S. Sankararaman,Preeti Gupta,Z. Zhang,G. Lo,Madhavan Swaminathan,Rao Tummala,Suresh K. Sitaraman,C.P. Wong,M. Iyer,Mihai Rotaru,Andrew A. O. Tay +17 more
TL;DR: In this paper, the effect of wafer level packaging, silicon substrate, and board material on gigabit data transmission was discussed, and a test vehicle consisting of a co-planar silicon transmission line, two board transmission lines and wafer-level packaging was used for evaluation.
Proceedings ArticleDOI
Advances in fine pitch lead free assembly process
R. Doraiswarni,S. Sankaxwaman,Woopoung Kim,Jing Li,Zhuqing Zhang,Preeti Gupta,K. Nakanishi,M. Borkar,R. Madhavan,V. Govind,Suna Choi,A.O. Aggarwal,Yangyang Sun,Lianhua Fan,V. Sundaram,Madhavan Swaminathan,C.P. Wong,Rao Tummala +17 more
TL;DR: In this paper, the authors focus on evolving the best possible criteria for selecting high electrical performance 100 micron pitch lead free solder bumping process, which is achieved through modeling and simulating the pad, process, reliability and test strategy Coplanar waveguides (CPW) were modeled to evolve process criteria for pad design and choice of materials Polyimide was chosen as the passivation on the chip Further signal parasitics were studied for the passivies and a selection criterion was evolved for its thickness.