The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-/spl mu/m embedded memory logic (EML) technology. Its area is 84 mm/sup 2/, and power consumption is 160 mW when all of the functions are activated.

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An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications

A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.

A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application

A single-chip MPEG4 video codec LSI with 20 Mb embedded DRAM performs a QCIF 15 Hz H.263 codec, a Simple at L1 codec, and Core at L1 decoding. It consumes 90 mW at 54 MHz. This chip integrates a programmable DSP, 8 dedicated hardware engines, and interface units on a 75.68 mm/sup 2/ die using 0.18 /spl mu/m 1.8 V quad-metal CMOS technology.

A 90 mW MPEG4 video codec LSI with the capability for core profile

A very low-power MPEG-4 video decoder LSI for mobile applications is presented. A 27-MHz 16-b DSP with a vector pipeline architecture, four 27-MHz dedicated hardware engines for accelerating MPEG-4 visual SP@L1 decoding and post video processing, 896 Kb of embedded SRAM for storing reference images and bitstreams, and three peripheral blocks are integrated together on a single chip. The architecture of the DSP is optimized in terms of power consumption and performance. MPEG-4 visual SP@L1 decoding and post-video processing at low operating frequencies are realized using a hybrid architecture consisting of the DSP and the dedicated hardware engines. Clock gating is used extensively to reduce the power consumption of the processor. The processor has high reusability because it does not use process-dependent technology such as V/sub DD/-hopping and variable threshold voltages. The chip is implemented using 0.18-/spl mu/m CMOS technology. Its die area is 37 mm/sup 2/ and the power consumption is 11 mW at 1.5 V.

A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications

We have developed a programmable DSP for MPEG4, H.263, H.261 and wavelet based sub-band codec algorithms. This DSP has the capability of processing these algorithms in real-time and has excellent flexibility, so that it can, for instance, perform video codec at 15 CIF frames/sec or video/speech (G.723.1) codec at 30 QCIF frames/sec. This chip includes a video pre/post-processing engine and needs only one 16 Mbit SDRAM as an external memory to perform the above algorithms, making it possible to realize low-cost systems. This chip is fabricated using 0.25 um CMOS technology and contains 7.7 M transistors on 9.41 mm/spl times/9.22 mm die.

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

We have developed a programmable video codec system using a video codec DSP called VDSP1 X for low-bit-rate communication which performs realtime encoding and decoding using discrete cosine transform (DCT)-based algorithms, such as ITU-T H.261, H.263, and wavelet-based subband encoding algorithms. This system realizes real time encoding and decoding for QCIF frame sizes for both DCT-based algorithms and wavelet-based subband encoding algorithms in the same environment.

J. Michiyama

Papers

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

A programmable video codec system for low-bit-rate communication