T
T. Hashimoto
Publications - 5
Citations - 85
T. Hashimoto is an academic researcher. The author has contributed to research in topics: Codec & Adaptive Multi-Rate audio codec. The author has an hindex of 4, co-authored 4 publications receiving 84 citations.
Papers
More filters
Proceedings ArticleDOI
A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application
M. Obashi,T. Hashimoto,S. Kuromaru,M. Matsuo,T. Mori-iwa,M. Hamada,Y. Sugisawa,M. Arita,H. Tomita,M. Hoshino,H. Miyajima,T. Nakamura,K. Ishida,T. Kimura,Y. Kohashi,T. Kondo,A. Inoue,H. Fujimoto,K. Watada,T. Fukunaga,T. Nishi,H. Ito,Junji Michiyama +22 more
TL;DR: A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation.
Proceedings ArticleDOI
A 90 mW MPEG4 video codec LSI with the capability for core profile
T. Hashimoto,S. Kuromaru,M. Matsuo,K. Yasuo,T. Mori-iwa,K. Ishida,S. Kajita,M. Ohashi,M. Toujima,T. Nakamura,M. Hamada,T. Yonezawa,T. Kondo,K. Hashimoto,Y. Sugisawa,H. Otsuki,M. Arita,H. Nakajima,H. Fujimoto,Junji Michiyama,Yasuo Iizuka,H. Komori,S. Nakatani,H. Toida,T. Takahashi,H. Ito,T. Yukitake +26 more
TL;DR: A single-chip MPEG4 video codec LSI with 20 Mb embedded DRAM performs a QCIF 15 Hz H.263 codec, a Simple at L1 codec, and Core at L2 decoding, and consumes 90 mW at 54 MHz.
Journal ArticleDOI
A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications
T. Hashimoto,M. Ohashi,M. Matsuo,S. Kuromaru,T. Mori-iwa,M. Hamada,Y. Sugisawa,H. Tomita,M. Hoshino,T. Nakamura,K. Ishida,K. Watada,T. Fukunaga,Junji Michiyama +13 more
TL;DR: A very low-power MPEG-4 video decoder LSI for mobile applications is presented and has high reusability because it does not use process-dependent technology such as V/sub DD/-hopping and variable threshold voltages.
Proceedings ArticleDOI
A MPEG4 programmable codec DSP with an embedded pre/post-processing engine
S. Kurohmaru,M. Matsuo,H. Nakajima,Y. Kohashi,T. Yonezawa,T. Mori-iwa,M. Ohashi,M. Toujima,T. Nakamura,M. Hamada,T. Hashimoto,H. Fujimoto,Y. Iizuka,J. Michiyama,H. Komori +14 more
TL;DR: This DSP has the capability of processing these algorithms in real-time and has excellent flexibility, so that it can, for instance, perform video codec at 15 CIF frames/sec or video/speech (G.723.1) codec at 30 QCIF frames/, making it possible to realize low-cost systems.