The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

This paper presents a cost-effective processor core design that features the simplest hardware and is suitable for discrete cosine transform/indiscrete cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two-dimensional DCT algorithm, the bit level adder-based distributed arithmetic, and common subexpression sharing to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easily scaled for higher throughput rate requirements. The DCT design has been implemented by 0.6 /spl mu/m SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm/sup 2/. The proposed design can meet real-time DCT/IDCT requirements of the H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional computing power for other operations when operating at 33 MHz.

https://ir.nctu.edu.tw:443/bitstream/11536/30625/1/000086613300013.pdf

A simple processor core design for DCT/IDCT

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-/spl mu/m embedded memory logic (EML) technology. Its area is 84 mm/sup 2/, and power consumption is 160 mW when all of the functions are activated.

/pdf/an-80-20-mhz-160-mw-multimedia-processor-integrated-with-4dv1cuckuo.pdf

An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

https://users.ece.utexas.edu/~adnan/comm/mpeg-jssc-03.pdf

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.

A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application

We have developed a video DSP which performs real-time encoding and decoding for DCT-based algorithms, such as ITU-T H.261, and wavelet-based subband encoding algorithms. This LSI is suitable for consumer applications as it was implemented using 0.5 /spl mu/m-CMOS process technology to realize compactness (1 million transistors on 65 mm/sup 2/) and low power(560 mW). It features a processing unit which performs wavelet filtering at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. At 40 MHz, a single chip is capable of processing QCIF size pictures at a rate of over 15 frames/second.

http://ieeexplore.ieee.org/iel3/3769/11004/00510575.pdf

A DSP for DCT-based and wavelet-based video codecs for consumer applications

We have developed a programmable DSP for MPEG4, H.263, H.261 and wavelet based sub-band codec algorithms. This DSP has the capability of processing these algorithms in real-time and has excellent flexibility, so that it can, for instance, perform video codec at 15 CIF frames/sec or video/speech (G.723.1) codec at 30 QCIF frames/sec. This chip includes a video pre/post-processing engine and needs only one 16 Mbit SDRAM as an external memory to perform the above algorithms, making it possible to realize low-cost systems. This chip is fabricated using 0.25 um CMOS technology and contains 7.7 M transistors on 9.41 mm/spl times/9.22 mm die.

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

We have developed a video digital signal processor (VDSP1) which performs real-time encoding and decoding for discrete cosine transform- (DCT-) based algorithms such as ITU-T H.261, H.263 and wavelet-based subband encoding algorithms. This LSI is suitable for consumer applications, as it was implemented using 0.5 /spl mu/m CMOS process technology to realize compactness (one million transistors on 65 mm/sup 2/) and low power (maximum: 560 mW). It features a processing unit which performs wavelet filtering at high speeds, a compact DCT circuit, and a fast, flexible DRAM interface for low-cost systems. At 40 MHz, a single chip is capable of processing quarter common intermediate format (QCIF) (176/spl times/144 pixels) size pictures at a rate greater than 15 frames/s.

T. Yonezawa

Papers

A DSP for DCT-based and wavelet-based video codecs for consumer applications

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

A DSP for DCT-based and wavelet-based video codecs for consumer applications