In the coming ubiquitous-IT society, low-power design is one of the key features at which the VLSI designer should aim. Otherwise, power increase will remain as one of the main obstacles to Moore's law growth. Unless VLSI power is lowered by orders of magnitude, we cannot enjoy the progress that scaling offers. This talk will cover what we now have, and what we should provide in our low-power armory to allow us to cope with ever-increasing leakage loss, as well as dynamic power. The techniques to be presented range over the system, software, circuit, and device levels including interconnect and I/O issues. The novel trend is to examine cooperative approaches between levels such as software-circuit cooperation and circuit-technology cooperation. The biggest challenge that System-on-Chip designers must resolve in the future is the fact that transistors for digital and memory circuits will be more and more leaky as technology generations advance. Approaches to solving this serious problem will be described. Beyond the quest for low-power solutions lies a promising world of ubiquitous VLSI devices and products ranging from "wireless sensors and tags for everything" to "everything-you-must-do mobile terminals".

Perspectives on power-aware electronics

The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

This paper provides a survey of state-of-the-art hardware architectures for image and video coding. Fundamental design issues are discussed with particular emphasis on efficient dedicated implementation. Hardware architectures for MPEG-4 video coding and JPEG 2000 still image coding are reviewed as design examples, and special approaches exploited to improve efficiency are identified. Further perspectives are also presented to address the challenges of hardware architecture design for advanced image and video coding in the future.

Advances in Hardware Architectures for Image and Video Coding - A Survey

The paper covers techniques to cope with ever-increasing leakage power as well as dynamic power of CMOS VLSI’s. The techniques to be presented range from software, system, circuit to device level. The novel trend is to look into the cooperative approaches between disciplines such as software-circuit cooperation and circuit-technology cooperation. The biggest challenge that System-on-a-Chip designers should meet in the future is the fact that transistors go more and more leaky in digital and memory circuits as generation advances. The topics to break through this stringent problem are described. Approaches to lower power at the system level are also discussed. The paper touches on new applications and markets which will be open up by the low-power VLSI’s. key words: digital, memory, application, low power, VLSI, leakage

Perspectives of Low-Power VLSI's

A 121-mm/sup 2/ graphics LSI is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics and MPEG-4 applications. The LSI contains a RISC processor with a multiply-accumulate unit (MAC), a 3-D rendering engine, a programmable power optimizer, and 29-Mb embedded DRAM. The chip is built in a 0.16-/spl mu/m pure DRAM technology to reduce the fabrication cost. Texture-mapped 3-D graphics with perspective-correct address calculation and bilinear MIPMAP filtering can be realized while consuming the low power with the help of depth-first clock gating, address alignment logic, and embedded DRAM. Programmable clocking allows the LSI to operate in lower power modes for various applications. The chip consumes less than 210 mW, delivering 66 Mpixels/s and 264 Mtexel/s texture-mapped pixels with real-time special effects such as full-scene antialiasing and motion blur.

/pdf/a-210-mw-graphics-lsi-implementing-full-3-d-pipeline-with-1kp1mpqyxf.pdf

A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications

A single-chip MPEG-4 video decoder LSI with integrated 896 kb embedded SRAM frame buffer and embedded video display engine consumes 11.1 mW at 27 MHz operation. The chip achieves QCIF 15 Hz H.263 and Simple@L1 decoding capability on a 37.26 mm/sup 2/ die using 0.18 μm 1.5 V quad-metal CMOS technology.

A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application

We have developed a programmable DSP for MPEG4, H.263, H.261 and wavelet based sub-band codec algorithms. This DSP has the capability of processing these algorithms in real-time and has excellent flexibility, so that it can, for instance, perform video codec at 15 CIF frames/sec or video/speech (G.723.1) codec at 30 QCIF frames/sec. This chip includes a video pre/post-processing engine and needs only one 16 Mbit SDRAM as an external memory to perform the above algorithms, making it possible to realize low-cost systems. This chip is fabricated using 0.25 um CMOS technology and contains 7.7 M transistors on 9.41 mm/spl times/9.22 mm die.

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

We have developed a programmable video codec system using a video codec DSP called VDSP1 X for low-bit-rate communication which performs realtime encoding and decoding using discrete cosine transform (DCT)-based algorithms, such as ITU-T H.261, H.263, and wavelet-based subband encoding algorithms. This system realizes real time encoding and decoding for QCIF frame sizes for both DCT-based algorithms and wavelet-based subband encoding algorithms in the same environment.

Y. Kohashi

Papers

A 27 MHz 11.1 mW MPEG-4 video decoder LSI for mobile application

A MPEG4 programmable codec DSP with an embedded pre/post-processing engine

A programmable video codec system for low-bit-rate communication