This paper summarizes some of the essential aspects of silicon-nanowire growth and of their electrical properties. In the first part, a brief description of the different growth techniques is given, though the general focus of this work is on chemical vapor deposition of silicon nanowires. The advantages and disadvantages of the different catalyst materials for silicon-wire growth are discussed at length. Thereafter, in the second part, three thermodynamic aspects of silicon-wire growth via the vapor–liquid–solid mechanism are presented and discussed. These are the expansion of the base of epitaxially grown Si wires, a stability criterion regarding the surface tension of the catalyst droplet, and the consequences of the Gibbs–Thomson effect for the silicon wire growth velocity. The third part is dedicated to the electrical properties of silicon nanowires. First, different silicon nanowire doping techniques are discussed. Attention is then focused on the diameter dependence of dopant ionization and the influence of interface trap states on the charge carrier density in silicon nanowires. It is concluded by a section on charge carrier mobility and mobility measurements.

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Silicon Nanowires: A Review on Aspects of their Growth and their Electrical Properties

2.4. Molecular Beam Epitaxy 366 2.5. Laser Ablation 367 2.6. Silicon Monoxide Evaporation 367 3. Catalyst Materials 368 3.1. Gold as Catalyst 368 3.2. Alternative Catalyst Materials 369 3.2.1. Type-A, Au-like Catalysts 370 3.2.2. Type-B, Low Si Solubility Catalysts 371 3.2.3. Type-C, Silicide Forming Catalysts 371 4. Crystallography 372 5. Heterostructures 373 6. Surface Induced Lowering of the Eutectic Temperature 375

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Growth, thermodynamics, and electrical properties of silicon nanowires.

Advancements in scaling gate insulators for MOS transistors permit low-voltage, silicon-oxide-nitride-silicon (SONOS) nonvolatile semiconductor memories (NVSMs) for a wide range of applications. The continued scaling of SONOS devices offers improved performance with a small cell size, single-level polysilicon with low voltage, fast erase/write, improved memory retention, increased endurance, and radiation hardness. In this article, we discuss scaled SONOS devices, SONOS memory technology, and some SONOS NVSM applications.

On the go with SONOS

A unified treatment of the basic electrostatic and dynamic design of charge-coupled devices (CCD's) based on approximate analytical analysis is presented. Clocking methods and tradeoffs are discussed. Driver power dissipation and on-chip power dissipation are analyzed. Properties of noise sources due to charge input and transfer are summarized. Low-noise methods of signal extraction are discussed in detail. The state of the art for linear and area arrays is presented. Tradeoffs in area-array performance from a systems point of view and performance predictions are presented in detail. Time delay and integration (TDI) and the charge-injection device (CID) are discussed. Finally, the uses of the charge-coupled concept in infrared imaging are discussed.

Imaging devices using the charge-coupled concept

The charge retention characteristics in scaled SONOS nonvolatile memory devices with an effective gate oxide thickness of 94 A and a tunnel oxide of 15 A are investigated in a temperature range from room temperature to 175°C. Electron charge decay rate is sensitive to the temperature, whereas hole charge decay rate remains essentially constant. Based on experimental observations and an amphoteric trap model for nitride traps, an analytical model for charge retention of the excess electron state is developed. Using this thermal activated electron retention model, the trap distribution in energy within the nitride film is extracted.

Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures

A direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors. Charge transport in the erase/write mode of operation is interpreted in terms of the device threshold voltage shift. The threshold voltage shift in the erase/write mode is related to the amplitude and time duration of the applied gate voltage over the full range of switching times. MNOS memory devices ( X_{o}=25 \Aring, X_{N} = 335 \Aring ) exhibit a \Delta V_{th} = \plusmn3 V for an erase/write t_{p} = 100 ns, which corresponds to an initial oxide field strength E_{ox}= 1.2 \times 10^{7} V/cm. The direct tunneling theory is applied to the charge retention or memory mode in which charge is transported to and from the Si-SiO 2 interface states. The rate of charge loss to interface states is influenced by electrical stress which alters the interface state characteristics. We discuss the fabrication of complementary high-speed MNOS memory transistors and the experimental test procedures to measure charge transport and storage in these devices.

J.R. Cricchi

Papers

Characterization of thin-oxide MNOS memory transistors