Characterization of thin-oxide MNOS memory transistors

TLDR: In this paper, a direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors.

Abstract: A direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors. Charge transport in the erase/write mode of operation is interpreted in terms of the device threshold voltage shift. The threshold voltage shift in the erase/write mode is related to the amplitude and time duration of the applied gate voltage over the full range of switching times. MNOS memory devices ( X_{o}=25 \Aring, X_{N} = 335 \Aring ) exhibit a \Delta V_{th} = \plusmn3 V for an erase/write t_{p} = 100 ns, which corresponds to an initial oxide field strength E_{ox}= 1.2 \times 10^{7} V/cm. The direct tunneling theory is applied to the charge retention or memory mode in which charge is transported to and from the Si-SiO 2 interface states. The rate of charge loss to interface states is influenced by electrical stress which alters the interface state characteristics. We discuss the fabrication of complementary high-speed MNOS memory transistors and the experimental test procedures to measure charge transport and storage in these devices.