We consider the feasibility of fabricating planar superconductor‐semiconductor‐superconductor Josephson junctions in which the junction supercurrent is controlled by a gate electrode isolated from the junction by either a dielectric film (MOS‐JOFET) or a Schottky barrier (MES‐JOFET). We find that device critical currents between ∼1 and 100 μA and critical temperatures approximately a few K appear possible. We discuss the circuit applications of such devices.

Feasibility of hybrid Josephson field effect transistors

Remarkable developments in bipolar technology over the past decade have seen the silicon germanium heterojunction bipolar transistor emerge from research labs to enter production in radio frequency technologies. These developments have allowed SiGe BiCMOS transistors to address high frequency wireless and optical communications applications that were previously only possible in III/V and II/VI devices. This book brings together for the first time all the new developments and describes in a unified manner the physics, materials science and technology of silicon bipolar transistors and SiGe heterojunction bipolar transistors.

https://leseprobe.buch.de/images-adb/cc/68/cc681325-f4d0-46db-9ce8-2f97a1b2bc3e.pdf

SiGe Heterojunction Bipolar Transistors

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm2/V.s and drain breakdown voltage exceeding 15 V.

Fully isolated lateral bipolar&#8212;MOS transistors fabricated in zone-melting-recrystallized Si films on SiO 2

A process for forming high performance npn bipolar transistors in an enhanced CMOS process using only one additional mask level. The bipolar transistor is formed using a low dose blanket implant to form the base in the substrate n-well, then applying arsenic-implanted polysilicon to form the emitter. The emitter formation involves forming a blanket polysilicon layer over the wafer, then using the additional photomask to confine the subsequent arsenic implant to the emitter, n + and polysilicon contact regions, prior to application of aluminum metallization. The arsenic implanted polysilicon technique provides state-of-the-art bipolar processing as well as improved contact characteristics. The combined polysilicon-aluminum metallization improves step coverage, circuit reliability, and reduces the possibility of aluminum diffusion (spiking) through junctions. The n-type contact resistance is improved by virtue of being implanted with arsenic; the p-type contact resistance is controlled by the diffusion from the p + regions which dope the polysilicon during the emitter drive-in cycle.

Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor

In this paper, rules are presented for the optimized design of CMOS-bipolar drivers for large capacitive loads typical of VLSI interconnects. Simulations and closed-form solutions show that the n-p-n bipolar transistors have to be operated in the high-level injection mode, and that their sizes have to be tailored to the two-thirds power of the load, and it scales with the two-thirds power of the base width of the n-p-n transistor and with the one-third power of the channel length of the MOS transistor. For comparison, the CMOS cascade with a tailored second stage is shown to have competitive potential at the expense of an area being approximately 2.5 times larger than that of a CMOS-bipolar stage.

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

An MOS LSI technology is presented, which allows the efficient fabrication of n-MOS and CMOS circuits on the same chip, a capability, which has become highly desirable in view of recent advances in circuit design, particularly analog-digital interfaces. The process starts from a p-type substrate. An n-well is formed by ion implantation. An additional implantation simultaneously sets the p-channel and n-channel threshold voltages as well as the field threshold above the substrate. The implanted field provides high density and simple processing. A third implantation step adjusts the threshold voltage of the n-channel depletion load transistor. Supply voltages up to 20 V are possible. Process modeling data are presented both by theoretical consideration and the measurement of actual profiles of the well and threshold dependence on energy, dose, and drive-in conditions. Distributions of the electrical parameters are rather narrow with standard deviations of thresholds <150 mV. Transconductance constants are typically 9 and 29 µA . V-2for p-and n-channel transistors, respectively. CMOS inverter gain is 250 for channel lengths of 10 and 25 µm, respectively.

A compatible NMOS, CMOS metal gate process

A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are ± 1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 µAV-2. The bipolar transistors have a low-resistance base contact. Current gain β F can be set independently. For \beta_{F} = 90 , the Early voltage is V_{A} = 110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.

An advanced LSI process is presented which puts high-performance, high-density n-MOS enhancement/depletion, CMOS and npn bipolar transistors on the same chip in order to realize on-chip systems with combined analog and digital functions. The process involves 6 masks for structure definition and up to 3 photoresist masks for selective implants. Doping is done exclusively by implantation. Standard deviations of MOS threshold voltages are < 100 mV, bipolar current gains can be set between 60 and 300. Sheet resistances of the source and drain as well as the inactive base regions are low for high-frequency performance and high levels of integration. Field threshold and breakdown voltages exceed 25 V.

http://ieeexplore.ieee.org/iel5/9943/31771/01479305.pdf

Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors

A simple d.c. method is presented for the extraction of very shallow doping profiles in the depth range 0?200 nm in buried-channel transistors or c.c.d.s. The evaluation is free from complex corrections. Profile position and concentrations are determined with ± 5% accuracy.

J. Schneider

Papers

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

A compatible NMOS, CMOS metal gate process

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

Advanced compatible LSI process for N-MOS, CMOS and bipolar transistors

Extraction of implantation profiles from the differential body effect of ion-implanted m.o.s. transistors