High-voltage Al/sub 0.22/Ga/sub 0.78/N-GaN high-electron mobility transistors have been fabricated using multiple field plates over dielectric passivation layers. The device breakdown voltage was found to increase with the addition of the field plates. With two field plates, the device showed a breakdown voltage as high as 900 V. This technique is easy to apply, based on the standard planar transistor fabrication, and especially attractive for the power switching applications.

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High breakdown voltage AlGaN-GaN HEMTs achieved by multiple field plates

A high electron mobility transistor (HEMT) is disclosed that includes a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an active structure of aluminum gallium nitride on the gallium nitride layer, a passivation layer on the aluminum gallium nitride active structure, and respective source, drain and gate contacts to the aluminum gallium nitride active structure.

Nitride based transistors on semi-insulating silicon carbide substrates

A simple and efficient method of GaAs FET amplifier analysis is presented. The FET is represented by its circuit-type nonlinear dynamic model taking into account the device's main nonlinear effects including gate-drain voltage breakdown. An identification procedure for extraction of the model parameters is described in detail and examples are given. The calculation of the amplifier response to a single-input harmonic signal is performed using the piecewise harmonic balance technique. As this technique is rather time-consuming in its original form, the optimization routine used to solve the network equations was replaced by the Newton-Raphson algorithm. Characteristics calculated with the use of the proposed method are compared with experimental data taken for a microwave amplifier using a 2SK273 GaAs FET unit. Good agreement at 9.5 GHz over wide ranges of bias voltage and input power levels are observed.

Computer Calculation of Large-Signal GaAs FET Amplifier Characteristics

A theory that emphasizes the role of surface states in the operation of GaAs MESFETs and that is intended to tie together hitherto unconnected anomalies in device behavior is presented. Such undesirable effects are consistent with the DC and microwave characteristics of the FET being modified by charge exchange with surface states. Generally speaking, these states are relatively slow, having characteristics frequencies of typically 1 kHz, but they nevertheless affect the microwave scattering parameters of the FET through the distortion they introduce to the shape of the depletion region in the transistor under given bias conditions. It is argued that the FET structure behaves as natural 'probe' of surface states and so constitutes a useful analytic tool for studying states on a variety of unpassivated and passivated surfaces. >

Low-field low-frequency dispersion of transconductance in GaAs MESFETs with implications for other rate-dependent anomalies

As a basis for designing GaAs MESFET's for broad-band low-noise amplifiers, the fundamental relationships between basic device parameters, and two-port noise parameters are investigated in a semiempirical manner. A set of four noise parameters are shown as simple functions of equivalent circuit elements of a GaAs MESFET. Each element is then expressed in a simple analytical form with the geometrical and material parameters of this device. Thus practical expressions for the four noise parameters are developed in terms of the geometrical and material parameters. Among the four noise parameters, the minimum noise figure F/sub min/, and equivalent noise resistance R/sub n/, are considered crucial for broad-band Iow-noise amplifiers. A low R/sub n/ corresponds to less sensitivity to input rnismatch, and can be obtained with a short heavily doped thin active channel. Such a high channel doping-to-thickness (N/a) ratio has a potential of producing high power gain, but is contradictory to obtaining a low F/min/. Therefore, a compromise in choosing N and a is necessary for best overall amplifier performance. Four numerical examples are given to show optimization processes.

Design of Microwave GaAs MESFET's for Broad-Band Low-Noise Amplifiers

The onset of gate-drain avalanche imposes an important fundamental constraint on the drain voltage swing, and hence, on the output power of GaAs FET's. In this paper we show that recognition of the role of surface depletion and proper attention to channel design can yield avalanche voltage factors of 2-3 above bulk values. The appropriate design strategy is minimization of the undepleted epitaxial charge per unit area (Q u ) between gate and drain, which, in turn, dictates a gate-notch depth approximately equal to the surface zero-bias depletion depth. A simple lateral spreading model is proposed which predicts that V_{L} \sim 50Q\min{u}\max{-1} , where V L is the gate-drain avalanche voltage and Q u is measured in units of 1012electrons/cm2. This prediction is supported by a large body of experimental dc and pulse data, although considerable scatter is observed which we have attributed to epi charge nonuniformities, premature avalanche at the rough edges of AI gates formed by a liftoff process, and surface charging variations associated with dielectric passivation. The observed dependence of V L on epi charge rather than on doping level, as predicted for bulk avalanche, provides convincing evidence for nonbulk two-dimensional avalanche in the thin-film ( Q_{u} ) FET geometry. In thick films ( Q_{u} > 2.6 ), on the other hand, it is found that the bulk avalanche predictions are reasonably accurate. In terms of saturated epi current I s , the bulk regime corresponds to I_{s} > 450 mA/mm and the lateral spreading (thin-film) regime to I_{s} mA/mm. Finally, we have found that gate-drain avalanche is the major cause of output saturation as a function of drain potential in power GaAs FET's.

Control of gate&#8212;Drain avalanche in GaAs MESFET's

Catastrophic source-drain burnout is an important failure mode in GaAs power FET's. In this paper we show that short-term (instantaneous) and long-term (aging) failures have different physical origins provided the underlying drain ohmic-contact weakness has been suppressed by use of a recessed n+drain ledge geometry. With this drain configuration, instantaneous burnout is due to thermal runaway of the buffer/substrate when local temperatures reach the 500-550°C range. For our typical devices With 30-50-µm-thick substrates, the associated de burnout power is 4-5 W/mm of gate periphery. Long-term aging failure, on the other hand, results from chemical changes at the GaAs surface between gate and drain. These changes induce localized areas of avalanche white-light emission, particularly along the n+ledge, which serve as burnout precursors. A series of aging, surface etching, and passivation experiments has revealed that oxygen probably plays a major role in the aging process, perhaps through its known effect on free arsenic formation. Moreover, it is found that minimization of the oxygen content at the top surface by using si 3 N 4 :H passivation rather than SiO 2 not only prevents white-light emission but increases the median life at 310°C channel temperature from 2.5 to more than 500 h.

Long-term and instantaneous burnout in GaAs power FET's: Mechanisms and solutions

Gallium arsenide power dissipating devices are described, which comprise an array of mesas formed on a plated heat sink in order to reduce thermal effects. The array is connected in parallel with beam leads to permit thermocompression bonding to only one of the mesas and thus reduce the number of bonding operations. Bonding stresses to the device may be eliminated by rendering one of the mesas inactive.

Gallium arsenide schottky barrier avalance diode array

MBE growth of epitaxial layers on selected areas of a growth surface (e.g., wafer or epi-layer grown thereon) is achieved by masking portions of the surface with an amorphous material and directing molecular beams at the masked surface so that a polycrystalline layer deposits on the mask and an epi-layer grows in the unmasked zones. The mask material is then exposed to a suitable etchant effective to dissolve that material, lift-off the polycrystalline layer and expose the underlying surface. Self-aligned contacts can be fabricated by depositing a metal layer prior to etching. Subsequent lift-off removes both the polycrystalline layer and the overlying metal. This process can be utilized in the fabrication of FETs and opto-electronic devices such as double heterostructure junction lasers.

Selective lift-off technique for fabricating gaas fets

The low‐noise FET’s prepared on molecular‐beam‐epitaxial (MBE) layers have a noise figure of 1.9 dB with a corresponding gain of 11 dB at 6 GHz. The power FET’s can produce 1.3 W at 4.4 GHz (1‐dB compression) with a gain of 10 dB and a power‐added efficiency of 35%. The influence of substrate preparation on Hall mobility for very thin layers was also studied and there is no evidence of Cr diffusion from the substrate at the MBE growth temperature.

J.V. DiLorenzo

Papers

Control of gate—Drain avalanche in GaAs MESFET's

Long-term and instantaneous burnout in GaAs power FET's: Mechanisms and solutions

Gallium arsenide schottky barrier avalance diode array

Selective lift-off technique for fabricating gaas fets

Low‐noise and high‐power GaAs microwave field‐effect transistors prepared by molecular beam epitaxy

J.V. DiLorenzo

Papers

Control of gate&#8212;Drain avalanche in GaAs MESFET's

Long-term and instantaneous burnout in GaAs power FET's: Mechanisms and solutions

Gallium arsenide schottky barrier avalance diode array

Selective lift-off technique for fabricating gaas fets

Low‐noise and high‐power GaAs microwave field‐effect transistors prepared by molecular beam epitaxy

Control of gate—Drain avalanche in GaAs MESFET's