Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.

This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.

http://www.umiacs.umd.edu/~joseph/classes/enee640/fpga-dsp-survey.pdf

Reconfigurable Computing for Digital Signal Processing: A Survey

A systematic folding transformation technique to fold any arbitrary signal processing algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set and specified technology constraints, is presented. The folding set specifies the processor and the time partition at which the task is executed and is typically obtained by performing scheduling and resource allocation for the algorithm data-flow graph and the specified iteration period. The constraints imposed on the hardware architecture are also assumed to be known. The technique is used to derive the control circuitry of the hardware architecture. The authors derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators. They propose automatic retiming and pipelining of algorithms described by data-flow graphs for folding. The folding algorithm is applied after preprocessing the data-flow graph for automated pipelining and retiming. >

Synthesis of control circuits in folded pipelined DSP architectures

A systematic unfolding transformation technique for transforming bit-serial architecture into equivalent digit-serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-serial architectures. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-serial architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed. >

A systematic approach for design of digit-serial signal processing architectures

A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design constraint. Another programmatic method synthesizes a processor array from the set of parallel processes and a specified design constraint.

Programmatic synthesis of processor element arrays

Embedded-system specification and design consists of describing a system's desired functionality and mapping that functionality for implementation by a set of system components such as processors, ASICs, memories, and buses. This paper discusses the key problems of system specification and design, including specification capture, design exploration, hierarchical modeling, software and hardware synthesis, and cosimulation. The authors highlight existing tools and methods for solving those problems and describe a "specify-explore-refine" methodology for meeting today's embedded-system product development requirements. >

Specification and design of embedded hardware-software systems

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process, from system specifications to integrated circuit layout, is carried out with the aid of specialized computer programs for the analysis, synthesis, and optimization at each design level: the filter network, the architecture, and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed which is integrated using a 5-/spl mu/m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis and optimization aids at each design level it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput, and moderate power consumption.

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

Describes the concepts and the status of the CATHEDRAL-II silicon compiler for digital signal processing systems. It is shown that efficient layout synthesis is possible, starting from a very high-level behavioural description of a system, owing to the careful definition of a target architectural design style and an application domain. An overview is presented of the different synthesis tools which have been or are being developed, both for architectural synthesis and optimisation, and for module and layout generation. With the underlying design methodology, the world of silicon design will become accessible to system engineers.

CATHEDRAL II—a computer-aided synthesis system for digital signal processing VLSI systems

The computer-aided design of a VLSI PCM-FDM transmultiplexer is presented. The entire design process from system specifications to integrated circuit layout is carried out with the aid of specialized computer programs for analysis, synthesis and optimization at each design level: the filter network, the architecture and the circuit layout. These CAD tools support a top-down custom design methodology based on bit-serial architectures and standard cells. A customized architecture is constructed, which is integrated using a 5- \mu m CMOS cell library. The results are compared with a fully manual design and demonstrate the power of architecture based computer-aided design methodologies for VLSI filtering. By combining both synthesis as well as optimization aids at each design level, it is possible to achieve a high degree of automation while retaining an efficient use of silicon area, high throughput and moderate power consumption.

J. Vanhoof

Papers

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system

CATHEDRAL II—a computer-aided synthesis system for digital signal processing VLSI systems

Custom design of a VLSI PCM-FDM transmultiplexer from system specifications to circuit layout using a computer-aided design system