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J.W. May

Researcher at University of California, San Diego

Publications -  9
Citations -  553

J.W. May is an academic researcher from University of California, San Diego. The author has contributed to research in topics: W band & Power gain. The author has an hindex of 7, co-authored 9 publications receiving 536 citations.

Papers
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Journal ArticleDOI

A Millimeter-Wave (40–45 GHz) 16-Element Phased-Array Transmitter in 0.18- $\mu$ m SiGe BiCMOS Technology

Kwang-Jin Koh, +2 more
- 02 May 2009 - 
TL;DR: This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications, based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network.
Journal ArticleDOI

Design and Characterization of $W$ -Band SiGe RFICs for Passive Millimeter-Wave Imaging

J.W. May, +1 more
- 25 Mar 2010 - 
TL;DR: In this paper, the authors describe the design and measurement of a wideband (W-band) passive radiometer chip developed in a standard 0.12-?m SiGe BiCMOS technology (IBM8HP, ft /fmax = 200/265 GHz).
Proceedings ArticleDOI

High-performance W-band SiGe RFICs for passive millimeter-wave imaging

J.W. May, +1 more
TL;DR: A W-band square-law detector was implemented in a commercial SiGe 0.12µm BiCMOS process (IBM8HP, f t = 200 GHz) and was integrated with a SiGe LNA and SPDT switch as mentioned in this paper.
Proceedings ArticleDOI

A 3 G-Bit/s W-band SiGe ASK receiver with a high-efficiency on-chip electromagnetically-coupled antenna

J.W. May, +2 more
TL;DR: In this article, a W-band microstrip antenna was designed in a commercial SiGe process (IBM 8HP) with a measured gain of 2-4 dB and an efficiency of 50-57% at 92-98 GHz.
Journal ArticleDOI

A 40-50-GHz SiGe 1 : 8 differential power divider using shielded broadside-coupled striplines

J.W. May, +1 more
- 23 May 2008 - 
TL;DR: In this article, a 1 : 8 differential power divider is implemented in a commercial SiGe BiCMOS process using fully shielded broadside-coupled striplines integrated vertically in the silicon interconnect stackup.