High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

The growing packing density and power consumption of very large scale integration (VLSI) circuits have made thermal effects one of the most important concerns of VLSI designers The increasing variability of key process parameters in nanometer CMOS technologies has resulted in larger impact of the substrate and metal line temperatures on the reliability and performance of the devices and interconnections Recent data shows that more than 50% of all integrated circuit failures are related to thermal issues This paper presents a brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power VLSI circuits The paper is concluded with an overview of techniques to improve the full-chip thermal integrity by means of off-chip versus on-chip and static versus adaptive methods

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Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods

In many new high performance designs, the leakage component of power consumption is comparable to the switching component. Reports indicate that 40% or even higher percentage of the total power consumption is due to the leakage of transistors. This percentage will increase with technology scaling unless effective techniques are introduced to bring leakage under control. This article focuses on circuit optimization and design automation techniques to accomplish this goal. The first part of the article provides an overview of basic physics and process scaling trends that have resulted in a significant increase in the leakage currents in CMOS circuits. This part also distinguishes between the standby and active components of the leakage current. The second part of the article describes a number of circuit optimization techniques for controlling the standby leakage current, including power gating and body bias control. The third part of the article presents techniques for active leakage control, including use of multiple-threshold cells, long channel devices, input vector design, transistor stacking to switching noise, and sizing with simultaneous threshold and supply voltage assignment.

Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits

It has been the conventional assumption that, due to the superlinear dependence of leakage power consumption on temperature, and widely varying on-chip temperature profiles, accurate leakage estimation requires detailed knowledge of thermal profile. Leakage power depends on integrated circuit (IC) thermal profile and circuit design style. The authors show that linear models can be used to permit highly-accurate leakage estimation over the operating temperature ranges in real ICs. The authors then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have similar impact on the average temperature of the layer. These two observations allow us to prove that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with linear leakage power consumption models, permit highly-accurate system-wide leakage power consumption estimation. The results of our proofs are further confirmed via comparisons with leakage estimation based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that the proposed technique yields a 59,259times-1,790,000times speedup in leakage power estimation while maintaining accuracy

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Accurate temperature-dependent integrated circuit leakage power estimation is easy

Accurate measurements and degradation mechanisms of the channel mobility for MOSFETs with HfO/sub 2/ as the gate dielectric have been systematically studied in this paper. The error in mobility extraction caused by a high density of interface traps for a MOSFET with high-k gate dielectric has been analyzed, and a new method to correct this error has been proposed. Other sources of error in mobility extraction, including channel resistance, gate leakage current, and contact resistance for a MOSFET with ultrathin high-k dielectric have also been investigated and reported in this paper. Based on the accurately measured channel mobility, we have analyzed the degradation mechanisms of channel mobility for a MOSFET with HfO/sub 2/ as the gate dielectric. The mobility degradation due to Coulomb scattering arising from interface trapped charges, and that due to remote soft optical phonon scattering are discussed.

Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics

Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed This model has been implemented in BSIM4

J.X. An

Papers

BSIM4 gate leakage model including source-drain partition