W
Wen-Chin Lee
Researcher at University of California, Berkeley
Publications - 46
Citations - 5531
Wen-Chin Lee is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Gate oxide & MOSFET. The author has an hindex of 23, co-authored 46 publications receiving 5336 citations. Previous affiliations of Wen-Chin Lee include TSMC & Hitachi.
Papers
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Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Proceedings ArticleDOI
Sub 50-nm FinFET: PMOS
Xuejue Huang,Wen-Chin Lee,C. Kuo,D. Hisamoto,Leland Chang,J. Kedzierski,E. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
Patent
Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
Chenming Hu,Tsu-Jae King,Vivek Subramanian,Leland Chang,Xuejue Huang,Yang-Kyu Choi,Jakub Tadeusz Kedzierski,Nick Lindert,Jeffrey Bokor,Wen-Chin Lee +9 more
TL;DR: In this article, a planar MOSFET is fabricated in a silicon layer overlying an insulating layer (e.g., SIMOX) with the device extending from the insulating layers as a fin.
Journal ArticleDOI
Sub-50 nm P-channel FinFET
Xuejue Huang,Wen-Chin Lee,C. Kuo,Digh Hisamoto,Leland Chang,J. Kedzierski,Erik H. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects, which shows good performance down to a gate-length of 18 nm.
Journal ArticleDOI
Modeling CMOS tunneling currents through ultrathin gate oxide due to conduction- and valence-band electron and hole tunneling
Wen-Chin Lee,Chenming Hu +1 more
TL;DR: In this paper, a semi-empirical model is proposed to quantify the tunneling currents through ultrathin gate oxides (1-3.6 nm) as a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), gate materials (N/sup +/, P/sup+/, Si, SiGe) and tunneling processes.