Proceedings ArticleDOI
BSIM4 gate leakage model including source-drain partition
K.M. Cao,Wen-Chin Lee,Weidong Liu,Xiaodong Jin,Pin Su,S.K.H. Fung,J.X. An,B. Yu,Chenming Hu +8 more
- pp 815-818
TLDR
In this article, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed, which has been implemented in BSIM4 and BSIM3.Abstract:
Gate dielectric leakage current becomes a serious concern as sub-20 /spl Aring/ gate oxide prevails in advanced CMOS processes Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage In this work, an analytical intrinsic gate leakage model for MOSFET with physical source/drain current partition is developed This model has been implemented in BSIM4read more
Citations
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Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Journal ArticleDOI
Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods
Massoud Pedram,Shahin Nazarian +1 more
TL;DR: A brief discussion of key sources of power dissipation and their temperature relation in CMOS VLSI circuits, and techniques for full-chip temperature calculation with special attention to its implications on the design of high-performance, low-power V LSI circuits is presented.
Journal ArticleDOI
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
Farzan Fallah,Massoud Pedram +1 more
TL;DR: Circuit optimization and design automation techniques are introduced to bring leakage under control in CMOS circuits and present techniques for active leakage control.
Proceedings ArticleDOI
Accurate temperature-dependent integrated circuit leakage power estimation is easy
TL;DR: In this article, the authors show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have similar impact on the average temperature of the layer.
Journal ArticleDOI
Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics
TL;DR: In this paper, the degradation of channel mobility due to Coulomb scattering arising from interface trapped charges, and remote soft optical phonon scattering are discussed, as well as channel resistance, gate leakage current, and contact resistance for a MOSFET with ultrathin high-k dielectric.
References
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Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation
K.F. Schuegraf,Chenming Hu +1 more
TL;DR: In this paper, a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 /spl Aring/ and 130 /spl Ring/, is presented, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses.
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Hiroki Sasaki,Mizuki Ono,Takashi Yoshitomi,Tatsuya Ohguro,S. Nakamura,Masanobu Saito,Hiroshi Iwai +6 more
TL;DR: In this paper, a 1.5 nm direct-tunneling gate oxide was used to achieve a transconductance of more than 1,000 mS/mm at a gate length of 0.09 /spl mu/m at room temperature.
Proceedings ArticleDOI
Hole injection oxide breakdown model for very low voltage lifetime extrapolation
K.F. Schuegraf,Chenming Hu +1 more
TL;DR: In this article, an anode hole injection model for silicon dioxide breakdown characterization is presented for a large thickness range between 2.5 nm and at least 13 nm, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses.
Proceedings ArticleDOI
Modeling gate and substrate currents due to conduction- and valence-band electron and hole tunneling [CMOS technology]
Wen-Chin Lee,Chenming Hu +1 more
TL;DR: In this paper, a model is proposed to quantify the tunneling currents through ultra-thin gate oxides, which can accurately predict the gate and substrate currents and all the subcomponents in dual-gate CMOS devices.
Journal ArticleDOI
Thickness limitations of SiO/sub 2/ gate dielectrics for MOS ULSI
Peter Wright,Krishna C. Saraswat +1 more
TL;DR: The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined in this paper, where it is shown that a poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required.
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