Jack DiLullo

TL;DR: POWER5/sup TM/ is the next generation of IBM's POWER microprocessors, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support.

TL;DR: POWER5/sup TM/ is the next generation of IBM's POWER microprocessors, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support.

TL;DR: The most critical methodology innovations specific to POWER7 design are described, which were in modularity, timing closure, and design efficiency.

TL;DR: In this article, the authors present a method, system, and computer program product for executing timing analysis of an asynchronous clock domain crossing, based on the signal group associated with the signal.

TL;DR: In this paper, the authors present a static timing analysis (STA) run with shortened clock cycles to model full cycle clock variability, which is used to adjust slack data for all half cycle data paths (HCDP) to account for the additional half cycle variation (AHCV) and half cycle clock edge variability that may penalize the design model results in a real hardware implementation.