Minimum Cardinality Matrix Decomposition into Consecutive-Ones Matrices: CP and IP Approaches.- Connections in Networks: Hardness of Feasibility Versus Optimality.- Modeling the Regular Constraint with Integer Programming.- Hybrid Local Search for Constrained Financial Portfolio Selection Problems.- The "Not-Too-Heavy Spanning Tree" Constraint.- Eliminating Redundant Clauses in SAT Instances.- Cost-Bounded Binary Decision Diagrams for 0-1 Programming.- YIELDS: A Yet Improved Limited Discrepancy Search for CSPs.- A Global Constraint for Total Weighted Completion Time.- Computing Tight Time Windows for RCPSPWET with the Primal-Dual Method.- Necessary Condition for Path Partitioning Constraints.- A Constraint Programming Approach to the Hospitals / Residents Problem.- Best-First AND/OR Search for 0/1 Integer Programming.- A Position-Based Propagator for the Open-Shop Problem.- Directional Interchangeability for Enhancing CSP Solving.- A Continuous Multi-resources cumulative Constraint with Positive-Negative Resource Consumption-Production.- Replenishment Planning for Stochastic Inventory Systems with Shortage Cost.- Preprocessing Expression-Based Constraint Satisfaction Problems for Stochastic Local Search.- The Deviation Constraint.- The Linear Programming Polytope of Binary Constraint Problems with Bounded Tree-Width.- On Boolean Functions Encodable as a Single Linear Pseudo-Boolean Constraint.- Solving a Stochastic Queueing Control Problem with Constraint Programming.- Constrained Clustering Via Concavity Cuts.- Bender's Cuts Guided Large Neighborhood Search for the Traveling Umpire Problem.- A Large Neighborhood Search Heuristic for Graph Coloring.- Generalizations of the Global Cardinality Constraint for Hierarchical Resources.- A Column Generation Based Destructive Lower Bound for Resource Constrained Project Scheduling Problems.

Integration of AI and OR techniques in constraint programming for combinatorial optimization problems : 4th International Conference, CPAIOR 2007, Brussels, Belgium, May 23-26, 2007 : proceedings

The invention details methods and apparatus for a routing system or router that includes a model. The model can be in many different forms including but not limited to: resolution enhancement technologies such as OPC; lithography model including but not limited to aerial image; pattern-dependent functions; functions for timing/signal integrity/power; manufacturing process variations; and measured silicon data. In one embodiment, the model can be described as input to the system and the model calculator can interact either with the data structure or the query engine of the detail router or both. The model calculator can accept input as a set of geometry description and produce output to guide the query functions. An example technique called set intersection is disclosed herein to combine multiple models in the system. A preferred embodiment of this invention includes a full chip grid-based router being aware of manufacturability.

Apparatus for a routing system

In this work, we present a learning-based approach to chip placement, one of the most complex and time-consuming stages of the chip design process. Unlike prior methods, our approach has the ability to learn from past experience and improve over time. In particular, as we train over a greater number of chip blocks, our method becomes better at rapidly generating optimized placements for previously unseen chip blocks. To achieve these results, we pose placement as a Reinforcement Learning (RL) problem and train an agent to place the nodes of a chip netlist onto a chip canvas. To enable our RL policy to generalize to unseen blocks, we ground representation learning in the supervised task of predicting placement quality. By designing a neural architecture that can accurately predict reward across a wide variety of netlists and their placements, we are able to generate rich feature embeddings of the input netlists. We then use this architecture as the encoder of our policy and value networks to enable transfer learning. Our objective is to minimize PPA (power, performance, and area), and we show that, in under 6 hours, our method can generate placements that are superhuman or comparable on modern accelerator netlists, whereas existing baselines require human experts in the loop and take several weeks.

Chip Placement with Deep Reinforcement Learning

The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates represent horizontal and vertical directions. A local placement grid of coordinates is also formed for at least one local region, where the local placement grid of coordinates represent horizontal and vertical directions, and where the at least one local region is adapted to support non-integer multiple height rows. At least one cell is associated with the at least one local region formed, and the cell can be placed in the local placement grid of the local region.

Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout

Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields. Machine learning tools are used to greatly accelerate chip layout design, by posing chip floorplanning as a reinforcement learning problem and using neural networks to generate high-performance chip layouts.

A graph placement methodology for fast chip design

We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement. In this framework, optimization is adaptive to current placement conditions through a new density metric. As a baseline, we leverage a recently developed at quadratic optimization that is comparable to prior multilevel frameworks in quality and runtime. A novel component called Progressive Local Refinement (ProLR) helps mitigate disruptions in wirelength that we observed in leading placers. Our placer MAPLE outperforms published empirical results --- RQL, SimPL, mPL6, NTUPlace3, FastPlace3, Kraftwerk and APlace3 -- across the ISPD 2005 and ISPD 2006 benchmarks, in terms of official metrics of the respective contests.

https://web.eecs.umich.edu/~imarkov/pubs/conf/ispd12-maple.pdf

MAPLE: multilevel adaptive placement for mixed-size designs

Local routing congestion is becoming increasingly important as complex design rules make local pin access the bottle-neck for modern designs and routers. Since congestion analysis based on global routing does not model these effects, routability-driven placement and physical synthesis fail to alleviate local congestion. This work models routing congestion at the placement level in order to apply local congestion mitigation. We propose a local congestion metric that computes a "routing-difficulty" score for every cell in the design library. To disperse local congestion, we apply a suite of detailed placement techniques called MILOR (Movement, cell Inflation and Legalization, and Optimization within a Row). Experimental results show that our techniques can significantly improve routing quality on real industry designs from 65, 45, and 32 nanometer technologies.

New placement prediction and mitigation techniques for local routing congestion

An automated method and apparatus for positioning gate array circuits in an integrated circuit design An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits

Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design

As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for DRC violations. Therefore, a machine learning model for DRC hotspot prediction needs to consider both very high-resolution pin shape patterns and low-resolution layout information as input features. A new convolutional neural network technique, J-Net, is introduced for the prediction with mixed resolution features. This is a customized architecture that is flexible for handling various input and output resolution requirements. It can be applied at placement stage without using global routing information. This technique is evaluated on 12 industrial designs at 7nm technology node. The results show that it can improve true positive rate by 37%, 40% and 14% respectively, compared to three recent works, with similar false positive rates.

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network

Timing-driven placement is a critical step in nanometer-scale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a commonly used technique. This paper shows that such an approach can improve timing, but often degrades wire length and routability. Another problem with existing timing-driven placers is inconsistencies in the definition of timing closure. Approaches using linear programming are forced to make assumptions about the timing models that simplify the problem. To truly do timing-driven placement, the placer must be able to make queries to a real timing analyzer with incremental capabilities. This paper describes an incremental timing-driven placer called ITOP. Using accurate timing from an industrial static timer, ITOP integrates incremental timing closure optimizations like buffering and repowering within placement to improve design timing without degrading wire length and routability.Experimental results on a set of optimized industrial circuit netlists show that ITOP significantly outperforms conventional net-weight based timing-driven placement. In particular, on average, it obtains an improvement of over 47.45%, 9.88% and 5% in the worst slack, total negative slack and wire length as compared to the conventional flow.

http://home.engineering.iastate.edu/~cnchu/pubs/c58.pdf

Shyam Ramji

Papers

MAPLE: multilevel adaptive placement for mixed-size designs

New placement prediction and mitigation techniques for local routing congestion

Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network

ITOP: integrating timing optimization within placement