M
Mike Lee
Researcher at IBM
Publications - 8
Citations - 215
Mike Lee is an academic researcher from IBM. The author has contributed to research in topics: Microprocessor & Simultaneous multithreading. The author has an hindex of 5, co-authored 8 publications receiving 213 citations.
Papers
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Proceedings ArticleDOI
Design and implementation of the POWER5 microprocessor
Joachim Gerhard Clabes,Joshua Friedrich,Mark D. Sweet,Jack DiLullo,Sam Gat-Shang Chu,Donald W. Plass,James W. Dawson,Paul H. Muench,Larry Powell,Michael Stephen Floyd,Balaram Sinharoy,Mike Lee,Michael Normand Goulet,James Donald Wagoner,Nicole Schwartz,Steve Runyon,Gary Alan Gorman,Phillip J. Restle,Ronald Nick Kalla,Joseph McGill,Steve Dodson +20 more
TL;DR: POWERS offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support.
Journal ArticleDOI
Design and Implementation of the POWER6 Microprocessor
Benjamin Stolt,Yonatan Mittlefehldt,Sanjay Dubey,Gaurav Mittal,Mike Lee,Joshua Friedrich,Eric Fluhr +6 more
TL;DR: Some of the circuit methodology and implementation innovations used in the development of POWER6, with particular emphasis on custom, synthesized, register file and SRAM design, as well as the electrical characterizations performed in the lab are described.
Design and Implementation of the POWER5 TM Microprocessor
Joachim Gerhard Clabes,Joshua Friedrich,Mark D. Sweet,Jack DiLullo,Sam Gat-Shang Chu,Donald W. Plass,Paul D. Muench,Larry Powell,Michael Floyd,Balaram Sinharoy,Mike Lee,James Donald Wagoner,Nicole Schwartz,Steve Runyon,Gary E. Gorman,Phillip J. Restle,Ronald Nick Kalla,Joseph McGill,Steve Dodson +18 more
TL;DR: The 276M transistor processor is implemented in 130nm silicon-on-insulator technology with 8-level of Cu metallization and operates at >1.5 GHz.
Proceedings ArticleDOI
Design and implementation of the POWER5/spl trade/ microprocessor
Joachim Gerhard Clabes,Joshua Friedrich,Mark D. Sweet,Jack DiLullo,Sam Gat-Shang Chu,Donald W. Plass,J. Dawson,Paul H. Muench,L. Powell,Michael Stephen Floyd,Balaram Sinharoy,Mike Lee,M. Goulet,J. Wagoner,N. Schwartz,Steve Runyon,G. Gorman,Phillip J. Restle,Ronald Nick Kalla,J. McGill,S. Dodson +20 more
TL;DR: POWER5/sup TM/ is the next generation of IBM's POWER microprocessors, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support.
Proceedings ArticleDOI
Design and implementation of the POWER5/spl trade/ microprocessor
Joachim Gerhard Clabes,Joshua Friedrich,Mark D. Sweet,Jack DiLullo,Sam Gat-Shang Chu,Donald W. Plass,J. Dawson,Paul H. Muench,L. Powell,Michael Stephen Floyd,Balaram Sinharoy,Mike Lee,M. Goulet,J. Wagoner,N. Schwartz,Steve Runyon,G. Gorman,Phillip J. Restle,Ronald Nick Kalla,J. McGill,S. Dodson +20 more
TL;DR: POWER5/sup TM/ is the next generation of IBM's POWER microprocessors, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support.