In this paper, we propose a new memristorbased crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

In this work, real-time coefficient of friction (COF) analysis, in conjunction with a new method for approximating the Sommerfeld Number, is used to determine the extent of normal and shear forces during chemical mechanical planarization (CMP) and to help identify the tribology of the system. A new parameter termed the `tribological mechanism indicator' is defined and extracted from the resulting Stribeck curves. The information on COF, `tribological mechanism indicator' and inter-layer dielectric (ILD) removal rate results in a series of `universal' correlations to help identify polishing conditions for optimized pad life and removal rate. Results further show that abrasive concentration, surface texture and pad grooving dramatically shift the tribology of the system from boundary lubrication to partial lubrication. Trends are explained using several models based on area of contact between wafer and abrasive particles, the extent of lubricity of the system and the compliance of the pad in micro- and macro-scales.

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Fundamental Tribological and Removal Rate Studies of Inter-Layer Dielectric Chemical Mechanical Planarization

The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.

Fault Tolerant Network on Chip Switching With Graceful Performance Degradation

Since its acceptance as the adopted symmetric-key algorithm, the Advanced Encryption Standard (AES) and its recently standardized authentication Galois/Counter Mode (GCM) have been utilized in various security-constrained applications. Many of the AES-GCM applications are power and resource constrained and require efficient hardware implementations. In this paper, different application-specific integrated circuit (ASIC) architectures of building blocks of the AES-GCM algorithms are evaluated and optimized to identify the high-performance and low-power architectures for the AES-GCM. For the AES, we evaluate the performance of more than 40 S-boxes utilizing a fixed benchmark platform in 65-nm CMOS technology. To obtain the least complexity S-box, the formulations for the Galois Field (GF) subfield inversions in GF(24) are optimized. By conducting exhaustive simulations for the input transitions, we analyze the average and peak power consumptions of the AES S-boxes considering the switching activities, gate-level netlists, and parasitic information. Additionally, we present high-speed, parallel hardware architectures for reaching low-latency and high-throughput structures of the GCM. Finally, by investigating the high-performance GF(2128) multiplier architectures, we benchmark the proposed AES-GCM architectures using quadratic and subquadratic hardware complexity GF(2128) multipliers. It is shown that the performance of the presented AES-GCM architectures outperforms the previously reported ones in the utilized 65-nm CMOS technology.

Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM

A bus for integrated circuits or embedded cores for serial access to circuits (e.g. for test, emulation, debug, trace operations) with limited pins. An integrated circuit (500) includes an IEEE 1149.1 Tap domain region (522) with Tap domains (502-508) having JTAQ circuits (510) coupled to an addressable Tap domain selection circuit (514) via buses (512). The selection circuit is coupled to a TDI input (520), a TCK input (516), a TMS input (518), and a TDO output (520).

Reduced signaling interface method & apparatus

For a system-on-a-chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper we introduce a simple flag based wrapped core linking module (WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Compared with other state-of-art techniques, our technique requires no modification to each core, uses less area, and provides more diverse link configurations.

A simple wrapped core linking module for SoC test access

A test interface controller (TIC) provided by ARM Ltd. is widely used for functional testing of system-on-a-chip (SoC) which adopts an advanced microcontroller bus architecture (AMBA) bus system. Unfortunately, this architecture has the deficiency of not being able to concurrently shift in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based test access mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. Since scan-in and out operations can be performed simultaneously, test application time on the expensive automatic test equipment (ATE) can be drastically reduced while preserving the compatibility with the ARM TIC.

Design of Test Access Mechanism for AMBA-Based System-on-a-Chip

In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE- 1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.

Low-Cost Scan Test for IEEE-1500-Based SoC

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.

An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Today’s System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-tomarket requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

Jaehoon Song

Papers

A simple wrapped core linking module for SoC test access

Design of Test Access Mechanism for AMBA-Based System-on-a-Chip

Low-Cost Scan Test for IEEE-1500-Based SoC

An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge

Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC