Showing papers in "Journal of Semiconductor Technology and Science in 2014"

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

Abstract: In this paper, we propose a new memristorbased crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption

Ultraviolet Photodetection Properties of ZnO/Si Heterojunction Diodes Fabricated by ALD Technique Without Using a Buffer Layer

Abstract: The fabrication and characterization of a Si/ZnO thin film heterojunction ultraviolet photodiode has been presented in this paper. ZnO thin film of ~100 nm thick was deposited on Silicon (Si) wafer by atomic layer deposition (ALD) technique. The Photoluminescence spectroscopy confirms that as-deposited ZnO thin film has excellent visible-blind UV response with almost no defects in the visible region. The room temperature current-voltage characteristics of the n-ZnO thin film/p-Si photodiodes are measured under an UV illumination of 650

A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory

Abstract: Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the VT variation among cells and reduce the total programming time.

Charge Controlled Meminductor Emulator

Abstract: Emulations of memristor-family elements are very important, since their physical realizations are very difficult to achieve with recent technologies. Although some previous studies succeeded in designing memristor and memcapacitor emulators, no significant contribution towards meminductor emulator has been presented so far. The implementation of a meminductor emulator is very important, since real meminductors are not expected to appear in near future. We designed the first meminductor emulator whose inductance can be varied by an external current source without employing any memrisitve system. The principle of our architecture and its feasibility have been verified using SPICE simulation.

Energy-Efficient and High Performance CGRA-based Multi-Core Architecture

Abstract: Coarse-grained reconfigurable architecture (CGRA)-based multi-core architecture aims at achieving high performance by kernel level parallelism (KLP). However, the existing CGRA- based multi-core architectures suffer from much energy and performance bottleneck when trying to exploit the KLP because of poor resource utilization caused by insufficient flexibility. In this work, we propose a new ring-based sharing fabric (RSF) to boost their flexibility level for the efficient resource utilization focusing on the kernel-stream type of the KLP. In addition, based on the RSF, we introduce a novel inter-CGRA reconfiguration technique for the efficient pipelining of kernel-stream on CGRA-based multi-core architectures. Experimental results show that the proposed approaches improve performance by up to 50.62 times and reduce energy by up to 50.16% when compared with the conventional CGRA-based multi-core architectures.

Fault Diagnosis in Semiconductor Etch Equipment Using Bayesian Networks

Abstract: A Bayesian network (BN) based fault diagnosis framework for semiconductor etching equipment is presented. Suggested framework contains data preprocessing, data synchronization, time series modeling, and BN inference, and the established BNs show the cause and effect relationship in the equipment module level. Statistically significant state variable identification (SVID) data of etch equipment are preselected using principal component analysis (PCA) and derivative dynamic time warping (DDTW) is employed for data synchronization. Elman’s recurrent neural networks (ERNNs) for individual SVID parameters are constructed, and the predicted errors of ERNNs are then used for assigning prior conditional probability in BN inference of the fault diagnosis. For the demonstration of the proposed methodology, 300 mm etch equipment model is reconstructed in subsystem levels, and several fault diagnosis scenarios are considered. BNs for the equipment fault diagnosis consists of three layers of nodes, such as root cause (RC), module (M), and data parameter (DP), and the constructed BN illustrates how the observed fault is related with possible root causes. Four out of five different types of fault scenarios are successfully diagnosed with the proposed inference methodology.

Schottky Barrier Tunnel Field-Effect Transistor using Spacer Technique

Abstract: In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and shortchannel SBTFET .

High Performance p-type SnO thin-film Transistor with SiO x Gate Insulator Deposited by Low-Temperature PECVD Method

Abstract: We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal SiO₂, a plasma-enhanced chemical vapor deposition (PECVD) SiNx, a 150 ℃-deposited PEVCD SiO x , and a 300 ℃-deposited PECVD SiO x . Among the devices, the one with the 150℃-deposited PEVCD SiO x exhibits the best electrical performance including a high field-effect mobility (=4.86 cm²/Vs), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localizedtrap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

Analysis of Random Variations and Variation-Robust Advanced Device Structures

Abstract: In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

Abstract: Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (fT). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

Integrate-and-Fire Neuron Circuit and Synaptic Device with Floating Body MOSFETs

Abstract: We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has shortterm and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

Abstract: We design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulktype fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width (Wfin) and height (Hfin) of the fin as well as the channel doping concentration (Nch). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.

Modeling and Simulation of Line Edge Roughness for EUV Resists

Abstract: With the extreme ultraviolet (EUV) lithography, the performance limit of chemically amplified resists has recently been extended to 16-and 11-nm nodes. However, the line edge roughness (LER) and the line width roughness (LWR) are not reduced automatically with this performance extension. In this paper, to investigate the impacts of the EUVL mask and the EUVL exposure process on LER, EUVL is modeled using multilayer-thin-film theory for the mask structure and the Monte Carlo (MC) method for the exposure process. Simulation results demonstrate how LERs of the mask transfer to the resist and the exposure process develops the resist LERs.

A CMOS Envelope Tracking Power Amplifier for LTE Mobile Applications

Abstract: This paper presents an envelope tracking power amplifier using a standard CMOS process for the 3GPP long-term evolution transmitters. An efficiency of the CMOS power amplifier for the modulated signals can be improved using a highly efficient and wideband CMOS bias modulator. The CMOS PA is based on a two-stage differential common-source structure for high gain and large voltage swing. The bias modulator is based on a hybrid buck converter which consists of a linear stage and a switching stage. The dynamic load condition according to the envelope signal level is taken into account for the bias modulator design. By applying the bias modulator to the power amplifier, an overall efficiency of 41.7 % was achieved at an output power of 24 dBm using the 16-QAM uplink LTE signal. It is 5.3 % points higher than that of the power amplifier alone at the same output power and linearity.

A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

Abstract: A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in 0.18 ?m standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is 17.6 ppm/oC, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately 0.03 mm2.

Blistering Induced Degradation of Thermal Stability Al2O3 Passivation Layer in Crystal Si Solar Cells

Abstract: Different kinds of post-deposition annealing (PDA) by a rapid thermal process (RTP) are used to enhance the field-effect passivation of Al2O3 film in crystal Si solar cells. To characterize the effects of PDA on Al2O3 and the interface, metalinsulator semiconductor (MIS) devices were fabricated. The effects of PDA were characterized as functions of RTP temperature from 400~700 °C and RTP time from 30~120 s. A high temperature PDA can retard the passivation of thin Al2O3 film in c-Si solar cells. PDA by RTP at 400 °C results in better passivation than a PDA at 400 °C in forming gas (H2 4% in N2) for 30 minutes. A high thermal budget causes blistering on Al2O3 film, which degrades its thermal stability and effective lifetime. It is related to the film structure, deposition temperature, thickness of the film, and annealing temperature. RTP shows the possibility of being applied to the PDA of Al2O3 film. Optimal PDA conditions should be studied for specific Al2O3 films, considering blistering.

Effect of Basal-plane Stacking Faults on X-ray Diffraction of Non-polar (1120) a-plane GaN Films Grown on (1102) r-plane Sapphire Substrates

Abstract: We report the effect of basal-plane stacking faults (BSFs) on X-ray diffraction (XRD) of non-polar (1120) a-plane GaN films with different SiNx interlayers. Complete SiNx coverage and increased three-dimensional (3D) to two-dimensional (2D) transition stages substantially reduce BSF density. It was revealed that the Si-doping profile in the Sidoped GaN layer was unaffected by the introduction of a SiNx interlayer. The smallest in-plane anisotropy of the (1120) XRD ω-scan widths was found in the sample with multiple SiNx layers, and this finding can be attributed to the relatively isotropic GaN mosaic resulting from the increase in the 3D-2D growth step. Williamson-Hall (WH) analysis of the (h0h0) series of diffractions was employed to determine the c-axis lateral coherence length (LCL) and to estimate the mosaic tilt. The c-axis LCLs obtained from WH analyses of the present study’s representative a-plane GaN samples were well correlated with the BSFrelated results from both the off-axis XRD ω-scan and transmission electron microscopy (TEM). Based on WH and TEM analyses, the trends in BSF densities were very similar, even though the BSF densities extracted from LCLs indicated that the values were reduced by a factor of about twenty.

Load-Balance-Independent High Efficiency Single-Inductor Multiple-Output (SIMO) DC-DC Converters

Abstract: A single-inductor multiple-output (SIMO) DC-DC converter providing buck and boost outputs with a new switching sequence is presented. In the proposed switching sequence, which does not require any additional blocks, input energy is delivered to outputs continuously by flowing current through the inductor, which leads to high conversion efficiency regardless of the balance between the buck and boost output loads. Furthermore, instead of multiple output loop compensation, only the freewheeling current feedback loop is compensated, which minimizes the number of off-chip components and nullifies the need for the equivalent series resistance (ESR) of the output capacitor for loop compensation. Therefore, power conversion efficiency and output voltage ripples can be improved and minimized, respectively. Implemented in a 0.35- μm CMOS, the proposed SIMO DC-DC converter achieves high conversion efficiency regardless of the load balance between the two outputs with maximum efficiency reaching up to 82% under heavy loads.

A Scan-Based On-Line Aging Monitoring Scheme

Abstract: In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.

A 256-Radix Crossbar Switch Using Mux-Matrix-Mux Folded-Clos Topology

Abstract: This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65㎚ CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-㎒ frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of 0.73-fJ/cycle·㎱·λ².

Effects of Ga Composition Ratio and Annealing Temperature on the Electrical Characteristics of Solution-processed IGZO Thin-film Transistors

Abstract: Bottom gate thin-film transistors were fabricated using solution processed IGZO channel layers with various gallium composition ratios that were annealed on a hot plate. Increasing the gallium ratio from 0.1 to 0.6 induced a threshold voltage shift in the electrical characteristics, whereas the molar ratio of In:Zn was fixed to 1:1. Among the devices, the IGZO-TFTs with gallium ratios of 0.4 and 0.5 exhibited suitable switching characteristics with low off-current and low SS values. The IGZO-TFTs prepared from IGZO films with a gallium ratio of 0.4 showed a mobility, on/off current ratio, threshold voltage, and subthreshold swing value of 0.1135 cm²/V·s, ~10 6 , 0.8 V, and 0.69 V/dec, respectively. IGZO-TFTs annealed at 300℃, 350℃, and 400℃ were also fabricated. Annealing at lower temperatures induced a positive shift in the threshold voltage and produced inferior electrical properties.

A PVT-compensated 2.2 to 3.0 GHz Digitally Controlled Oscillator for All-Digital PLL

Abstract: —We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of ±2.6% at 2.5 GHz. The DCO includes an 8 phase current-controlled ring oscillator, a digitally controlled current source (DCCS), a process and temperature (PT)-counteracting voltage regulator, and a bias current generator. The DCO operates at a center frequency of 2.5 GHz with a wide tuning range of 2.2 GHz to 3.0 GHz. At 2.8 GHz, the DCO achieves a phase noise of -112 dBc/Hz at 10 MHz offset. When it is implemented in an all-digital phase-locked loop (ADPLL), the ADPLL exhibits an RMS jitter of 8.9 ps and a peak to peak jitter of 77.5 ps. The proposed DCO and ADPLL are fabricated in 65 nm CMOS technology with supply voltages of 2.5 V and 1.0 V, respectively. Index Terms—Digitally controlled oscillator, ring oscillator, PVT compensated DCO, PT-counteracting voltage regulator, all-digital phase-locked loop

Bidirectional Transient Voltage Suppression Diodes for the Protection of High Speed Data Line from Electrostatic Discharge Shocks

Abstract: A bidirectional transient voltage suppression (TVS) diode consisting of specially designed p--n++-p-multi-junctions was developed using low temperature (LT) epitaxy and fabrication processes. Its electrostatic discharge (ESD) performance was investigated using IV, C-V, and various ESD tests including the human body model (HBM), machine model (MM) and IEC 61000-4-2 (IEC) analysis. The symmetrical structure with very sharp and uniform bidirectional multijunctions yields good symmetrical I-V behavior over a wide range of operating temperature of 300 K ? 450 K and low capacitance as 6.9 pF at 1 MHz. In addition, a very thin and heavily doped n++ layer enabled I-V curves steep rise after breakdown without snapback phenomenon, then resulted in small dynamic resistance as 0.2 ;, and leakage current completely suppressed down to pA. Manufactured bidirectional TVS diodes were capable of withstanding ± 4.0 kV of MM and ± 14 kV of IEC, and exceeding ± 8 kV of HBM, while maintaining reliable I-V characteristics. Such an excellent ESD performance of low capacitance and dynamic resistance is attributed to the abruptness and very unique profiles designed very precisely in p-n++p-multi-junctions.

A 120 GHz Voltage Controlled Oscillator Integrated with 1/128 Frequency Divider Chain in 65 nm CMOS Technology

Abstract: A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of 1385 × 835 μm².

Reducing Test Power and Improving Test Effectiveness for Logic BIST

Abstract: Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS’89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

Efficient Parallel Scan Test Technique for Cores on AMBA-based SoC

Abstract: Today’s System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-tomarket requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

An Enhanced Architecture of CMOS Phase Frequency Detector to Increase the Detection Range

Abstract: The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.

Pixel Circuit with Threshold Voltage Compensation using a-IGZO TFT for AMOLED

Abstract: A threshold voltage compensation pixel circuit was developed for active-matrix organic light emitting diodes (AMOLEDs) using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO-TFTs). Oxide TFTs are n-channel TFTs; therefore, we developed a circuit for the n-channel TFT characteristics. The proposed pixel circuit was verified and proved by circuit analysis and circuit simulations. The proposed circuit was able to compensate for the threshold voltage variations of the drive TFT in AMOLEDs. The error rate of the OLED current for a threshold voltage change of 3 V was as low as 1.5%.

Design of a CMOS Image Sensor Based on a 10-bit Two-Step Single-Slope ADC

Abstract: In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two step Single Slope A/D Converter (SS-ADC) is proposed. The A/D converter is composed of both 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D convertor. In order to reduce the pixel noise, further, a Hybrid Correlated Double Sampling (H-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA (320 x 240) resolution. The fabricated chip size is 5 mm x 3 mm, and the power consumption is about 35 mW at 3.3 V supply voltage. The measured conversion speed is 10 us, and the frame rate is 220 frames/s.