The method of the current invention provides a fault tolerant access to a network resource. A replicated network directory database operates in conjunction with server resident processes to remap a network resource in the event of a server failure. The records/objects in the replicated database contain for each network resource, a primary and a secondary server affiliation. Initially, all users access a network resource through the server identified in the replicated database as being the primary server for the network resource. When server resident processes detect a failure of the primary server, the replicated database is updated to reflect the failure of the primary server, and to change the affiliation of the network resource from its primary to its backup server. This remapping occurs transparently to whichever user/client is accessing the network resource. As a result of the remapping, all users access the network resource through the server identified in the replicated database as the backup server for the resource. When the server resident processes detect a return to service of the primary server, the replicated database is again updated to reflect the resumed operation of the primary server. This remapping of network resource affiliations also occurs transparently to whichever user/client is accessing the network resource, and returns the resource to its original fault tolerant state.

Method for providing a fault tolerant network using distributed server processes to remap clustered network resources to other servers during server failure

A system for fault tolerant execution of an application program in a server network, which includes: a first server for executing the application program; a cluster network database, coupled to the first server; an object, stored in the cluster network database, which represents the program and contains information pertaining to the program; a failure detection module which detects a failure of the first server; a second server, coupled to the cluster network database; and a failover module which loads the application program in the second server upon detection of the failure of the first server. The information contained within the object includes: a host server attribute which identifies which server is currently executing the program; a primary server attribute which identifies which server is primarily responsible for executing the program; and a backup server attribute which identifies which server is a backup server for executing the program if the primary server experiences a failure.

System for clustering software applications

A method for fault tolerant execution of an application program, in a server network having a first and second server, wherein the method includes: executing the application program in the first server; storing an object which represents the program in a cluster network database, wherein the object contains information pertaining to the program; detecting a failure of the first server; and executing the application program in the second server upon detection of the failure of the first server, in accordance with the information in the object. The information may include: a host server attribute which identifies which server is currently executing the program; a primary server attribute which identifies which server is primarily responsible for executing the program; and a backup server attribute which identifies which server is a backup server for executing the program if the primary server experiences a failure.

Method for clustering software applications

A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.

Diagnostic and managing distributed processor system

A software architecture for the hot add and swap of adapters. The software architecture allows users to replace failed components, upgrade outdated components, and add new functionality, such as new network interfaces, disk interface adapters and storage, without impacting existing users. The software architecture supports the hot add and swap of off-the-shelf adapters, including those adapters that are programmable.

Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver

An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

Address space architecture for multiple bus computer systems

A computer system having a plurality of devices which transmit and receive information over a channel is presented The system includes, in the preferred embodiment, a central arbitration control circuit and a local arbiter associated with each device contending for channel access Each local arbiter, corresponding to a device which desires channel access, generates a channel request signal to the central control circuit At the appropriate time when the channel becomes available, the central control circuit generates an arbitrate signal All local arbiters, then contending for channel access, compare the priority level on the arbitration bus with the priority value of the device it is arbitrating on behalf of, with the winning device gaining access to the channel Each of the local arbiters contains a programmable circuit which enables the arbiter to operate either utilizing a linear priority arbitration technique or a fairness priority arbitration technique Thus, each device is dynamically programmable to operate in a linear mode or a fairness mode depending on user and/or application needs Additionally, each local arbiter includes a circuit which detects whether the device is a burst transfer device or a single transfer device

Computer system having dynamically programmable linear/fairness priority arbitration scheme

An interrupt subsystem in a computer system processes shared level interrupts by direct transfer to the single correct interrupt service routine without an iterative transfer-of-control sequence. Direct transfer is accomplished by comparing data in a predetermined table with data retrieved from the I/O device 606. When a match is found, indicating the correct device, then control is transferred to the interrupt handler whose address is stored in the table 610. Provision is made for compatibility with pre-existing iterative transfer-of-control systems 608.

Method and apparatus for processing interrupts in a computer system

PURPOSE: To provide an address space architecture in a multiple bus information processing system and a bridge circuit for address conversion. CONSTITUTION: This information processing system is provided with a processor 12, a first bus 16 for transmitting a signal following a first bus protocol which does not support an I/O address signal, a second bus 19 for transmitting a signal following a second bus protocol supporting the I/O address signal and the bridge circuit 18 for connecting the first bus 16 to the second bus 19. The processor 12 is provided with a circuit for outputting an address signal and an address type signal to a selected peripheral equipment. The bridge circuit 18 is provided with a filter for judging whether the address signal outputted by the processor 12 corresponds to the peripheral equipment connected to the bus 19 in the lower layer of the bridge circuit 18 and a conversion circuit which is connected to the filter for transmitting the signals to the selected peripheral equipment and converts the signal following the first bus protocol into the signal following the second bus protocol.

James D. Reid

Papers

Address space architecture for multiple bus computer systems

Computer system having dynamically programmable linear/fairness priority arbitration scheme

Method and apparatus for processing interrupts in a computer system

Multiple bus information processing system and the bridge circuit