Patent
Address space architecture for multiple bus computer systems
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TLDR
In this paper, a bridge circuit is proposed for coupling the first bus to the second bus to determine whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit.Abstract:
An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.read more
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References
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Patent
Arbitration logic for multiple bus computer system
Nader Amini,Patrick Maurice Bland,Bechara Fouad Boury,Richard Gerard Hofmann,Terence J. Lohman +4 more
TL;DR: In this article, an arbitration mechanism is provided for use in a computer system which comprises a central processing unit (CPU), a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; and a second system bus connected to the CPU; a host bridge connecting the second system buses to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and an input/output (I/O) bridge connecting a standard I/O bus to a standard IO bus having a plurality of
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