The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16 , 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Integrated circuit I/O using a high performance bus interface

A system in which a single VLAN architecture spans multiple VLAN transport protocols and technologies, including a method and system in which multiple different VLANs may be combined in a single enterprise network. Each LAN-switch in the sytem identifies each frame with an identifier, and associates that identifier with particular VLAN identifiers for each type of VLAN technology. When a frame is bridged or routed from a first type of VLAN to a second type of VLAN, the first VLAN encapsulation is removed and the second VLAN encapsulation is added, with appropriate change in the VLAN identifier for the frame or packet. The identifier may also be implicit for the frame, such as when a particular set of sender's MAC addresses are identified with a particular VLAN. Individual VLANs, of whatever architecture, may be added, configured or reconfigured, modified, or deleted, using control tools associated with the multiple VLAN architecture system. Individual ports may be associated with particular VLANs, or may be designated "dynamic" so that frames or packets associated with those ports are associated with particular VLANs in response to source or destination addresses or other information.

Multiple VLAN architecture system

A number of systems and methods, alone, or in combination, achieve various levels of protection against unauthorized modification and distribution of digital content. This encompasses at least unauthorized study, modification, monitoring, reconstruction, and any other means for subversion from the originally intended purpose and license model of the digital content. The invention combines a number of techniques that in whole, or in part, serve to protect such content from unauthorized modification, reconstructive engineering, or monitoring by third parties. This is accomplished by means of methods which protect against subversion by specific tools operating on specific platforms as well as general tools operating on general platforms. Specific time domain attacks are identified, code modification can be identified and reversed, and virtual and emulated systems are identified. In addition, identification of in-circuit emulator tools (both software and hardware), debuggers, and security threats to running programs can be achieved.

Systems and methods for the prevention of unauthorized use and manipulation of digital content

A computerized system for dynamically and automatically configuring circuit boards to carry out functions from various manufacturers and a computer system without the user intervention. A single computer system may include, for example, a modem board, a video board, a disk controller board, and a multiple function board, each circuit board from a different manufacturer and each circuit board requires a computer resources for operation. These resources may include interrupt request (IRQ) lines, direct memory access (DMA) channels, I/O port addresses, memory address ranges and circuit board slot locations. The computerized system determines the type of slot required for each circuit board to be inserted in the computer by reading the circuit board configuration file for each board. The system will assign a circuit board to an available slot locations of the required type. Based on the information contained within the circuit board configuration files, the system attempts to allocate the common computer resources required by each circuit board based on the primary or default resource requirements set forth in each circuit board's configuration file. And, overlapping manufacturer default resource requirement may result in resource allocation conflict; and then, the system attempts to resolve conflicts by determining if the conflicting request may be assigned an alternate resource, as specified in the circuit board configuration file. The system stores the resource allocation information as part of a system configuration file which may then be used when the system is rebooted.

Computer implemented method and apparatus for dynamic and automatic configuration of a computer system and circuit boards including computer resource allocation conflict resolution

The invention provides a method and system for switching in networks responsive to message flow patterns. A message “flow” is defined to comprise a set of packets to be transmitted between a particular source and a particular destination. When routers in a network identify a new message flow, they determine the proper processing for packets in that message flow and cache that information for that message flow. Thereafter, when routers in a network identify a packet which is part of that message flow, they process that packet according to the proper processing for packets in that message flow. The proper processing may include a determination of a destination port for routing those packets and a determination of whether access control permits routing those packets to their indicated destination.

Network flow switching and flow data export

A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value. That portion of main memory containing the slot positions is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a nonvolatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the table to the card option registers if the status of all the slots has not not changed since the last power-down, system reset, or channel reset.

Method and apparatus for automatic initialization of pluggable option cards

A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value. That portion of main memory containing the slot positions is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a nonvolatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the table to the card option registers if the status of all the slots has not changed since the last power-down, system reset, or channel reset.

Computer system with automatic initialization of pluggable option cards

An information processing system comprises a processor, a first bus for conducting signals in accordance with a first bus protocol that does not support I/O address signals; a second bus for conducting signals in accordance with a second bus protocol that supports input/output (I/O) address signals; and a bridge circuit for coupling the first bus to the second bus. The processor includes a circuit for emitting address signals and an address type signal directed to a selected peripheral device. The bridge circuit comprises a filter for determining whether the address signal emitted by the processor corresponds to a peripheral device coupled to a bus subordinate to the bridge circuit; and a translation circuit, coupled to the filter, for translating signals in accordance with the first bus protocol to signals in accordance with the second bus protocol for transmission to the selected peripheral device.

Address space architecture for multiple bus computer systems

A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

Data processing system with pluggable option card

An arrangement and method for arbitration to enable split transaction bus protocols provides for a slave to assert a mask signal that sets a mask bit in a mask register when the slave is not ready to complete a requested transaction. A requesting master is forced off the bus and prevented from re-arbitrating while the mask bit is set in the register. When the slave is ready to complete the transaction, a release master signal is asserted which causes the bit in the shift register to be reset. The requesting master is then able to re-arbitrate for use of the bus to complete the transaction. The usable bandwidth of the bus is increased since other masters are able to arbitrate and use the bus until the slave is ready to complete the transaction with the first requesting master.

Ronald Eugene Valli

Papers

Method and apparatus for automatic initialization of pluggable option cards

Computer system with automatic initialization of pluggable option cards

Address space architecture for multiple bus computer systems

Data processing system with pluggable option card

Method and apparatus for arbitrating for a bus to enable split transaction bus protocols