Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing a silicon precursor to the deposition chamber, where the silicon precursor and the atomic oxygen precursor are first mixed in the chamber. The silicon precursor and the atomic oxygen precursor react to form the silicon oxide layer on the substrate, and the deposited silicon oxide layer may be annealed. Systems to deposit a silicon oxide layer on a substrate are also described.

Chemical vapor deposition of high quality flow-like silicon dioxide using a silicon containing precursor and atomic oxygen

The negative bias temperature instability in MOS devices: A review

Negative bias temperature instability (NBTI), in which interface traps and positive oxide charge are generated in metal–oxide–silicon (MOS) structures under negative gate bias, in particular at elevated temperature, has come to the forefront of critical reliability phenomena in advanced CMOS technology. The purpose of this review is to bring together much of the latest experimental information and recent developments in theoretical understanding of NBTI. The review includes comprehensive summaries of the basic phenomenology, including time- and frequency-dependent effects (relaxation), and process dependences; theory, including drift–diffusion models and microscopic models for interface states and fixed charge, and the role of nitrogen; and the practical implications for circuit performance and new gate-stack materials. Some open questions are highlighted. � 2005 Elsevier Ltd. All rights reserved.

Introductory Invited Paper The negative bias temperature instability in MOS devices: A review

Embodiments of the invention provide methods for depositing a capping layer on a dielectric layer disposed on a substrate. In one example, a process includes exposing a substrate to a deposition process to form a dielectric layer thereon, exposing the substrate to sequential pulses of a silicon precursor and an oxidizing gas to form a silicon-containing layer on the dielectric layer during a deposition process, exposing the substrate to a nitridation process to form a capping layer thereon and exposing the substrate to an annealing process for a predetermined time. The capping layer may a thickness of about 5 A or less. In one example, the oxidizing gas contains water vapor derived from a hydrogen source gas and an oxygen source gas processed by a water vapor generator containing a catalyst. In another example, the deposition, nitridation and annealing processes occur in the same process chamber.

Formation of a silicon oxynitride layer on a high-k dielectric material

A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.

High quality silicon oxide films by remote plasma cvd from disilane precursors

A method of fabricating a gate dielectric layer, including: providing a substrate (100); forming a silicon dioxide layer (110) on a top surface of the substrate (105); performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer (110A). The dielectric layer so formed may be used in the fabrication of MOSFETs (145).

Method for fabricating a nitrided silicon-oxide gate dielectric

The present invention relates to wear-through detection in multilayered parts. This invention specifically encompasses, in one aspect, wear-through detection in semiconductor vacuum processing systems in which a wear indicator that will release a detectable constituent upon exposure to processing conditions is used inside the semiconductor vacuum processing tool. This invention permits real time detection of wear during operation of semiconductor vacuum processing equipment.

Wear-through detector for multilayered parts and methods of using same

A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.

Method of fabricating a nitrided silicon oxide gate dielectric layer

A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.

Selective nitridation of gate oxides

Multi-layer SiN barrier film with high breakdown and low leakage is developed for Cu low k interconnects and is compared with the SiCNH barrier film used at previous technology nodes. Ultra-thin SiN barrier cap film also provides high conformality and fills recess in Cu lines observed post CMP. A significant enhancement in electro migration (EM) performance was obtained by selectively depositing Co on top of Cu lines followed by conformal multi-layer SiN barrier film. Further EM lifetime improvement is obtained by using a Co liner to form a wrap around structure with completely encapsulated Cu. An integrated in-situ preclean/ metal/dielectric cap chamber was used to avoid any oxidation of Cu/Co layers. Kinetic studies of CVD Co liner/Co cap samples show significant increase in EM activation energy (1.7 eV) over samples with dielectric only barrier film (0.9–1 eV). The complete wrap around structure with Co liner and Co cap shows improved device reliability.

Jay S. Burnham

Papers

Method for fabricating a nitrided silicon-oxide gate dielectric

Wear-through detector for multilayered parts and methods of using same

Method of fabricating a nitrided silicon oxide gate dielectric layer

Selective nitridation of gate oxides

Advanced metal and dielectric barrier cap films for Cu low k interconnects