J
John J. Ellis-Monaghan
Researcher at GlobalFoundries
Publications - 198
Citations - 2890
John J. Ellis-Monaghan is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Layer (electronics) & Transistor. The author has an hindex of 30, co-authored 198 publications receiving 2847 citations. Previous affiliations of John J. Ellis-Monaghan include IBM.
Papers
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Proceedings ArticleDOI
A 90nm CMOS integrated Nano-Photonics technology for 25Gbps WDM optical communications applications
Solomon Assefa,Steven M. Shank,William M. J. Green,Marwan H. Khater,Edward W. Kiewra,Carol Reinholm,Swetha Kamlapurkar,Alexander V. Rylyakov,Clint L. Schow,Folkert Horst,Huapu Pan,Teya Topuria,Philip M. Rice,Douglas M. Gill,Jessie Rosenberg,Tymon Barwicz,Min Yang,Jonathan E. Proesel,Jens Hofrichter,Bert Jan Offrein,Xiaoxiong Gu,Wilfried Haensch,John J. Ellis-Monaghan,Yurii A. Vlasov +23 more
TL;DR: The first sub-100nm technology that allows the monolithic integration of optical modulators and germanium photodetectors as features into a current 90nm base high-performance logic technology node is demonstrated.
Patent
Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
TL;DR: In this paper, a multiple fin fin-type field effect transistor (350) is described, in which the multiple fins arc partially or completely merged by a highly conductive material (i.e., a metal suicide).
Patent
Double planar gated SOI MOSFET structure
James W. Adkisson,John A. Bracchitta,John J. Ellis-Monaghan,Jerome B. Lasky,Effendi Leobandung,Kirk D. Peterson,Jed H. Rankin +6 more
TL;DR: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by using a mandrel shallow trench isolation formation process, followed by a damascene gate.
Proceedings ArticleDOI
Low-power CMOS at Vdd = 4kT/q
Andres Bryant,Jeffrey S. Brown,Peter E. Cottrell,Mark B. Ketchen,John J. Ellis-Monaghan,E.J. Nowak +5 more
TL;DR: In this paper, the authors reported a CMOS inverter active power-delay product of less than 0.1 fJ/stage at 25/spl deg/C and at Vdd=0.1 V.
Proceedings ArticleDOI
A 90nm SiGe BiCMOS technology for mm-wave and high-performance analog applications
John J. Pekarik,James W. Adkisson,Peter B. Gray,Q.Z. Liu,Renata Camillo-Castillo,Marwan H. Khater,Vibhor Jain,Bjorn Zetterlund,Adam W. Divergilio,Xiaowei Tian,Aaron L. Vallett,John J. Ellis-Monaghan,Blaine J. Gross,Peng Cheng,V. Kaushal,Zhong-Xiang He,J. Lukaitis,K. Newton,M. Kerbaugh,N. Cahoon,Leonardo Vera,Yi Zhao,John R. Long,Alberto Valdes-Garcia,Scott K. Reynolds,Wooram Lee,Bodhisatwa Sadhu,David L. Harame +27 more
TL;DR: The electrical characteristics of the first 90nm SiGe BiCMOS technology developed for production in IBM's large volume 200mm fabrication line are presented.