Showing papers by "Jean-Christophe Crebier published in 2017"

Characterization and Analysis of an Innovative Gate Driver and Power Supplies Architecture for HF Power Devices With High dv/dt

Abstract: This paper presents a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds. An electromagnetic interference (EMI) optimization is done by modifying the parasitic capacitance of the propagation paths between the power and the control sides, thanks to a specific design of the circuit. Moreover, to reduce the parasitic inductances and to minimize the antenna phenomenon, the paper studies which elements of the drivers’ circuitry must be brought as close as possible to the power parts. This is important when the ambient temperature of the power device becomes critical, for instance, in automotive and aeronautic applications. Simulations and experiments validate the advantages of the proposed architecture on the conducted EMI problem.

A New Step Towards the Power Electronics Design Automation

Abstract: This paper introduces the development of a generalized design and process flow dedicated to the design automation of power electronics converters. The proposed design methodology is based on power electronics building blocks (PEBB) approach together with a set of design rules allowing fast and secure design and prototyping of power converters. Compared to the regular PEBB approach where converters are produced associating pre-produced parts, our approach considers the blocks at design level, including the routing and the design factor optimization.

Higher switching speed of power devices in series connection achieved by modifying the gate driver architecture

Abstract: This paper presents the study on gate driver circuitries implemented to drive power devices in series connection with the objective to minimize the conducted EMI perturbations and as well to improve the switching speed of the power devices. More specifically, the propagation paths of parasitic currents generated under very high switching speed are studied in different configurations trying to reduce the parasitic capacitance of each gate driver circuit with respect to ground/control reference potential and to minimize the common mode currents. In complex power converters, multi-cell, multi-level or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points that are exiting the isolated barriers of the gate drivers (supplies and control signal isolation units) which mean that conducted EMI perturbations can be amplified and the switching speed of the power devices could be affected by multi-parasitic capacitances. Based on previous works, the paper analyses the best possible configurations to minimize the common mode currents in series connected transistor topologies and to reduce the parasitic capacitance of the gate driver circuitries leading as well to a significant improvement of the switching speed of the power devices. In this article, experimental validations are used to approve the analysis.

Analysis and prototyping of distributed series connected DC/AC converters integrated in PV panels

Abstract: This paper presents the design and the implementation of distributed, series connected DC/AC micro-converters in a multi panel/cell photovoltaic system for stand-alone applications. The proposed topology is based on the direct, low voltage DC/AC energy conversion at PV panel/cell level using micro-inverters, integrated in a standard CMOS ASIC. In such a way, they can be physically implemented into the junction box on the backside of each PV module, replacing the bypass diodes. This approach maximizes the amount of harvested energy thanks to the single stage conversion architecture and the individual maximum power point tracking (MPPT) for each PV module. Among other advantages, this distributed approach benefits from interleaved control strategies allowing down scaling of the volume of the output inductor and the EMI filters and offering an increased apparent switching frequency and a reduced current ripple. The experimental validation of the approach is carried out with a string of four low power PV tiles (10W).