High-performance gate drive power supply (GDPS) plays a crucial role in ensuring the reliability and safety of the gate driver for power semiconductor devices. This article focuses on the design of a high-voltage-insulated GDPS for the 10-kV silicon carbide MOSFET in medium-voltage (MV) application. Design considerations, including insulation scheme, high-voltage-insulated transformer design, and load voltage regulation scheme, are proposed. In addition, the performance of the secondary-side-regulated (SSR) GDPS and that of the primary-side-regulated (PSR) GDPS are compared for several aspects, including interwinding capacitance, load voltage regulation rate, conversion efficiency, and hardware complexity. Finally, an SSR GDPS and a PSR GDPS, with an insulation voltage of 20 kV, are built in the lab. The test results demonstrate that the PSR GDPS is more preferable because of lower interwinding capacitance, lower load voltage regulation rate, higher conversion efficiency, and simpler control circuit.

Design Considerations for High-Voltage Insulated Gate Drive Power Supply for 10-kV SiC MOSFET Applied in Medium-Voltage Converter

This paper presents a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds. An electromagnetic interference (EMI) optimization is done by modifying the parasitic capacitance of the propagation paths between the power and the control sides, thanks to a specific design of the circuit. Moreover, to reduce the parasitic inductances and to minimize the antenna phenomenon, the paper studies which elements of the drivers’ circuitry must be brought as close as possible to the power parts. This is important when the ambient temperature of the power device becomes critical, for instance, in automotive and aeronautic applications. Simulations and experiments validate the advantages of the proposed architecture on the conducted EMI problem.

Characterization and Analysis of an Innovative Gate Driver and Power Supplies Architecture for HF Power Devices With High dv/dt

Wide-bandgap devices have been widely used to reduce the size and increase the efficiency of power converters by operating at a high switching frequency, at the expense of heightened radiated and conducted electromagnetic inference (EMI) emissions, of which the latter circulates through the power loop and ancillary circuitry. In effect, the parasitic isolation capacitance $C_{i}$ of the gate-driver power supply represents a key EMI propagation path to be controlled in order to ensure the operational integrity of power converters. To this end, this paper proposes an integrated, dual-output gate-drive power supply for gallium-nitride (GaN) 650 V, 60 A, half-bridge phase legs, rated at 2 W (2 × 1 W), 15 to 2 × 7 V, featuring an ultralow $C_{i}$ of 1.6 pF, an output-to-output parasitic capacitance of 1.6 pF, a power density of 72 W/in3, and an efficiency of 85%. All this is attained using an active-clamp flyback converter switching at 1 MHz using 65 V GaN high-electron-mobility transistor devices and Schottky output rectifiers, and a Pareto-optimized transformer design minimizing its interwinding capacitances, volume, and losses. Finally, the transformer is fully embedded in a printed circuit board (PCB) material, doubling as a substrate for the topside active layer of the power supply. The paper presents the complete design procedure, processing, and experimental demonstration of the proposed integrated power supply, evaluating as well the reliability impact of the magnetic-PCB material interface in high ambient temperature applications (>200 °C).

Ultralow Input–Output Capacitance PCB-Embedded Dual-Output Gate-Drive Power Supply for 650 V GaN-Based Half-Bridges

This work presents a monolithic laterally-coupled wide-spectrum (350 nm < λ < 1270 nm) optical link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical abrupt n+p junctions, separated by a shallow trench isolation composed of silicon dioxide. Medium trench isolation around the devices along with the buried oxide layer provides galvanic isolation. Optical coupling in both avalanche-mode and forward-mode operation of the LED are analyzed for various designs and bias conditions. From both DC and pulsed transient measurements, it is further shown that heating in the avalanche-mode LED leads to a slow thermal coupling to the PD with time constants in the ms range. An integrated heat sink in the same technology leads to a ∼ 6 times reduction in the change in PD junction temperature per unit electrical power dissipated in the avalanche-mode LED. The analysis paves way for wide-spectrum optical links integrated in smart power technologies.

/pdf/monolithic-optical-link-in-silicon-on-insulator-cmos-4b2q76uubz.pdf

Monolithic optical link in silicon-on-insulator CMOS technology.

This paper presents a study on the gate driver circuitries that need to be implemented to drive several power devices when associated in series connection. More specifically, the propagation paths of parasitic currents through the gate driver circuitries, exited under high switching speeds, are studied in different configurations trying to minimize common mode currents generated. In a gate driver circuitry for a regular low side–high side switching cell configuration with one upper switch and one lower switch, the voltage transient dv/dt at the middle point applied across the primary-secondary parasitic capacitance of gate driver supplies, and control signal isolation units are the reasons for the generation of conducted electromagnetic interference (EMI) perturbations. In complex power converters, multicell, multilevel, or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points producing conducted EMI perturbations from the power part to the control part through many gate driver circuitries. Based on previous works, this paper analyzes the best configuration to minimize parasitic currents, especially reducing the conducted common mode currents in series connected transistors topologies. Simulations and practical results validate the analysis for two power devices in series connection, and then the extrapolations for more power devices in series connection, up to six are discussed and analyzed with the help of simulations results.

Gate Driver Supply Architectures for Common Mode Conducted EMI Reduction in Series Connection of Multiple Power Devices

In power converter configurations like multi-cell, multi-level, series connection of power devices etc. under very high switching speeds, several dv/dt sources generated at different floating points produce conducted EMI perturbations from the power part to the control part through the many gate driver circuitries. The modifications of the parasitic capacitive propagation paths between the power and the control sides have impacts on the circulating current produced by high dv/dt, which, in turns, affects the voltages distributions (static and transient) among the power devices. This paper presents news architectures for gate drivers power supplies implementations in series connection to minimize parasitic currents, especially reducing the common mode currents and to minimize the unbalance voltages of SiC-MOSFET devices in series connections. Simulations and experiments validate the advantages of the gate driver power supplies proposed architectures on the common mode currents and drain-to-source voltages of series-connected devices.

Gate Driver Architectures Impacts on Voltage Balancing of SiC MOSFETs in Series Connection

This paper introduces the implementation of a DC–AC step up isolated converter from associations of bidirectional Conversion Standard Cells (CSCs). The designed multi-cell converter is an array of standardized converter cells. It is described and then compared to a reference converter with respect to differential mode conducted electro-magnetic interference (EMI). The paper outlines the motivation for developing a generic multi-cell approach before underlining the benefits from the point of view of conducted EMI when implementing power converter arrays (PCAs). In particular, it is shown that in PCAs, the differential mode (DM) EMI filter can advantageously utilize distributed CSCs, making it possible to use very low value AC inductors to filter the AC current ripple. Experimental results are provided to validate the analysis carried out in the paper.

https://www.mdpi.com/2079-9292/8/9/999/pdf

DC-AC Isolated Power Converter Array. Focus on Differential Mode Conducted EMI

Based on WBG power devices operating constraints, this paper analyses and presents developments and prototyping of dedicated high side control signal level shifters. Designs take into account temperature, propagation delay deviation and high dv/dt susceptibility to deliver a generic solution able to comply with new device constraints. If silicon technology remains today the unique reliable technical solution, the implementation of gate driver in this technology is becoming very challenging. Delay deviations, signal integrity (duty cycle duration and time location) of prototypes are characterized with respect to temperature as well as dv/dt immunity.

Contributions to dedicated gate driver circuitry for very high switching speed high temperature power devices

This paper presents a study on the gate driver circuitries that need to be implemented to drive power devices in series connection. More specifically, the propagation paths of parasitic currents through the gate driver circuitries, generated under very high switching speed, are studied in different configurations trying to minimize common mode currents. In a gate driver circuitry for a regular low side - high side switching cell configuration with one upper switch and one lower switch, the voltage transient dv/dt at the middle point applied across the primarysecondary parasitic capacitance of gate driver supplies and isolation units are the reason of the conducted EMI perturbations. In complex power converters, multi-cell, multi-level or even series connection of power devices, many driver circuits are required and implemented. Similarly, in such converters, there are several dv/dt sources generated at different floating points producing conducted EMI perturbations from the power part to the control part through many gate driver circuitries. Based on previous works, the paper analyses the best configuration to minimize parasitic currents, especially reducing the common mode currents in series connected transistors topologies. Simulations and practical results validate the analysis.

Van-Sang Nguyen

Papers

Characterization and Analysis of an Innovative Gate Driver and Power Supplies Architecture for HF Power Devices With High dv/dt

Gate Driver Architectures Impacts on Voltage Balancing of SiC MOSFETs in Series Connection

DC-AC Isolated Power Converter Array. Focus on Differential Mode Conducted EMI

Contributions to dedicated gate driver circuitry for very high switching speed high temperature power devices

Gate Driver Architectures for High Speed Power Devices in Series Connection