This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters

This work presents and analyzes the design of a 1-V ultra-low power, compact, and wideband low-noise amplifier (LNA). The proposed LNA uses common-gate (CG) NMOS and PMOS transistors as input devices in a complementary current-reuse structure. Low power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor to improve the current efficiency of the LNA. A forward body biasing (FBB) scheme is exploited to tune the feedback coefficient. The complementary characteristics of the input stage leads to partial second-order distortion cancellation. The proposed inductorless LNA is implemented in an IBM 0.13- $\mu {\text {m}}~1$ P8M CMOS technology and occupies only $0.0052~{\text {mm}}^{2}$ . The measured LNA has a 12.3-dB gain 4.9-dB minimum noise figure (NF) input referred third-order intercept point (IIP3) of −10 dBm and 0.1–-2.2 GHz bandwidth (BW), while consuming only 400 $\mu {\text {A}}$ from a 1-V supply.

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

This paper proposes a new microstrip slow-wave structure. The unit cell comprises a Schiffman section of meander line and a shunt open-circuited stub. No via-holes and ground-plane patterns are required. Simple design formulas can be used to obtain line parameters, such as the characteristic impedance and phase velocity. According to the analysis, the characteristic impedance and slow-wave factor of the proposed slow-wave line can be independently controlled by merely two layout parameters. The proposed uniplanar structure only requires a single-layer substrate and is simply constructed using the conventional printed circuit board manufacturing process. A branch-line and a rat-race coupler were designed and fabricated using the proposed structure to demonstrate its feasibility. Their sizes are only 8.49% and 4.87% of the conventional ones, respectively. This novel slow-wave structure should find wide applications in compact microwave circuits.

/pdf/a-high-slow-wave-factor-microstrip-structure-with-simple-wgdy1129zj.pdf

A High Slow-Wave Factor Microstrip Structure With Simple Design Formulas and Its Application to Microwave Circuit Design

A fully integrated low-dropout-regulated step-down multiphase-switched-capacitor DC–DC converter (a.k.a. charge pump, CP) with a fast-response adaptive-phase (Fast-RAP) digital controller is designed using a 65-nm CMOS process. Different from conventional designs, a low-dropout regulator (LDO) with an NMOS power stage is used without the need for an additional step-up CP for driving. A clock tripler and a pulse divider are proposed to enable the Fast-RAP control. As the Fast-RAP digital controller is designed to be able to respond faster than the cascaded linear regulator, transient response will not be affected by the adaptive scheme. Thus, light-load efficiency is improved without sacrificing the response time. When the CP operates at 90 MHz with 80.3% CP efficiency, only small ripples would appear on the CP output with the 18-phase interleaving scheme, and be further attenuated at $V_{{\rm OUT}}$ by the 50-mV dropout regulator with only 4.1% efficiency overhead and 6.5% area overhead. The output ripple is less than 2 mV for a load current of 20 mA.

An NMOS-LDO Regulated Switched-Capacitor DC–DC Converter With Fast-Response Adaptive-Phase Digital Control

A low power Software-Defined radio receiver operating between 400MHz and 1.5GHz is presented, with the property to be robust to out-of-band blockers, thanks to the 4-path passive mixer architecture which acts as a high-Q bandpass filter for RF signals. The filter formed by the mixer at baseband fixes the receiver bandwidth at 10MHz. A common-gate cross-coupled LNA realizes a wideband input matching. The receiver works under 1.2V while consuming less than 10mW. The analog part consumes 4.8mW and the digital part consumes less than 5mW. The receiver has been implemented on a chip and occupies only 0.7mm2 silicon area.

http://ieeexplore.ieee.org/iel5/6410220/6421477/06421812.pdf

A 130nm low power Software-Defined radio receiver

A three-stage 60-GHz power amplifier was implemented in a 65 nm CMOS technology. High-quality-factor slow-wave coplanar waveguides were used for input, output and inter-stage matching networks in order to improve the performance. In Class-A operation, the power amplifier exhibits a measured maximum linear power gain G of 18.3 dB at 55 GHz, with a 3-dB bandwidth of 8.5 GHz. The measured 1-dB output compression point OCP 1dB and the maximum saturated output power P sat are 12 dBm and 14.2 dBm, respectively, with a DC power consumption of 156 mW under 1.2 V voltage supply. The measured peak power added efficiency PAE is 16 %. The die area is 0.52 mm2 (875 ×m × 600 μm) including all the pads, whereas the effective area is only 0.24 mm2.

Millimeter-wave CMOS power amplifier using slow-wave transmission lines

This paper presents a design-oriented MOS transistor model that uses only 7 parameters for analytically describing the MOSFET behavior. Based on the inversion charge, it accounts for the most relevant short-channel effects in advanced technologies. The model provides analytical relations for the transconductances, output conductance, and nonlinearities of the transistor for simple analytical circuit design. The model is validated using the 28nm FD-SOI technology from STMicroelectronics and is compared to a state-of-the-art 4-parameter model to demonstrate the advantages of the proposed model for RF/analog design purposes.

Jean-Michel Fournier

Papers

A 130nm low power Software-Defined radio receiver

Millimeter-wave CMOS power amplifier using slow-wave transmission lines

Design-oriented model for short-channel MOS transistors based on inversion charge