This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters

This work presents and analyzes the design of a 1-V ultra-low power, compact, and wideband low-noise amplifier (LNA). The proposed LNA uses common-gate (CG) NMOS and PMOS transistors as input devices in a complementary current-reuse structure. Low power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor to improve the current efficiency of the LNA. A forward body biasing (FBB) scheme is exploited to tune the feedback coefficient. The complementary characteristics of the input stage leads to partial second-order distortion cancellation. The proposed inductorless LNA is implemented in an IBM 0.13- $\mu {\text {m}}~1$ P8M CMOS technology and occupies only $0.0052~{\text {mm}}^{2}$ . The measured LNA has a 12.3-dB gain 4.9-dB minimum noise figure (NF) input referred third-order intercept point (IIP3) of −10 dBm and 0.1–-2.2 GHz bandwidth (BW), while consuming only 400 $\mu {\text {A}}$ from a 1-V supply.

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

This paper proposes a new microstrip slow-wave structure. The unit cell comprises a Schiffman section of meander line and a shunt open-circuited stub. No via-holes and ground-plane patterns are required. Simple design formulas can be used to obtain line parameters, such as the characteristic impedance and phase velocity. According to the analysis, the characteristic impedance and slow-wave factor of the proposed slow-wave line can be independently controlled by merely two layout parameters. The proposed uniplanar structure only requires a single-layer substrate and is simply constructed using the conventional printed circuit board manufacturing process. A branch-line and a rat-race coupler were designed and fabricated using the proposed structure to demonstrate its feasibility. Their sizes are only 8.49% and 4.87% of the conventional ones, respectively. This novel slow-wave structure should find wide applications in compact microwave circuits.

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A High Slow-Wave Factor Microstrip Structure With Simple Design Formulas and Its Application to Microwave Circuit Design

A fully integrated low-dropout-regulated step-down multiphase-switched-capacitor DC–DC converter (a.k.a. charge pump, CP) with a fast-response adaptive-phase (Fast-RAP) digital controller is designed using a 65-nm CMOS process. Different from conventional designs, a low-dropout regulator (LDO) with an NMOS power stage is used without the need for an additional step-up CP for driving. A clock tripler and a pulse divider are proposed to enable the Fast-RAP control. As the Fast-RAP digital controller is designed to be able to respond faster than the cascaded linear regulator, transient response will not be affected by the adaptive scheme. Thus, light-load efficiency is improved without sacrificing the response time. When the CP operates at 90 MHz with 80.3% CP efficiency, only small ripples would appear on the CP output with the 18-phase interleaving scheme, and be further attenuated at $V_{{\rm OUT}}$ by the 50-mV dropout regulator with only 4.1% efficiency overhead and 6.5% area overhead. The output ripple is less than 2 mV for a load current of 20 mA.

An NMOS-LDO Regulated Switched-Capacitor DC–DC Converter With Fast-Response Adaptive-Phase Digital Control

In this article, shielded coplanar striplines (S-CPS) are studied to achieve slow-wave transmission lines in a CMOS process. The slow-wave propagation is achieved by placing floating strips below the CPS transmission line. The propagation parameters of such transmission lines are derived by simulations by means of a “full wave” 3D EM software. Quality factors as high as 35 at 10 GHz together with effective dielectric constants of 78 are reported. If these simulation results are confirmed by measurements, this would open the door to the possible realization of integrated transmission line-based RF circuits such as power dividers, phase-shifters, or filters of medium bandwidth below 10 GHz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 352–358, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24054

Shielded coplanar striplines for RF integrated applications

A single-stage 60GHz class-A bipolar power amplifier (PA) is fabricated in a BiCMOS 55nm technology. In order to enhance the power added efficiency (PAE) behavior of the PA, a bias control loop, based on direct power detection, is implemented in order to dynamically adjust the DC bias current of the PA according to its output power level. A power detector (PD) is connected directly at the output of the amplifier in order to track the envelope variation of its output signal. The employed PD has a dynamic range of more than 30dB, and a maximum power consumption of 0.8mW. Under constant bias conditions, the PA has a power gain of around 7dB, a maximum PAE of 16%, and an output compression point of around 7.5dBm while driving 25.8mA under 1.2V supply voltage. Under adaptive bias control, the mean value of the DC current is reduced down to 20.8mA, while maintaining high power gain, leading to a significant enhancement of the PAE over the linear input dynamic range of the PA. System level simulations show that the applied technique enhances the average PAE and DC power consumption by 18% without significant discrepancies on the EVM, ACPR, and power gain.

Efficiency enhancement using adaptive bias control for 60GHz power amplifier

The vertical shrinkage of the advanced CMOS processes thicknesses makes electrostatic discharge (ESD) issues become more significant. RF and millimeter-wave (mm-wave) circuits are very sensitive to the ESD components’ capacitive parasitic effect. Surface area is a key factor as well in an ESD protection circuit for mm-wave applications. This paper presents silicon-verified ESD solutions, which fulfill physical dimensions, ESD robustness, and broadband frequencies requirements.

Generic Electrostatic Discharges Protection Solutions for RF and Millimeter-Wave Applications

This paper describes a V-Band power detector fabricated in a BiCMOS 55nm (ƒ t /ƒ max = 320GHz/370GHz) process. The detector is to be used in millimeter-wave circuits for automatic level control, built-in test and in-situ power measurement. The detector occupies an area of 0.0064mm2 and exhibits an equivalent input resistance/capacitance of 1kΩ /13fF around 60GHz. Measurements show a detection dynamic range of 30dB over the 50GHz to 66GHz bandwidth. The minimum detectable input power is −22dBm thanks to the use of common base bipolar SiGe transistor at the input stage. The measured output bandwidth is 700MHz. In nominal bias conditions, the detector power consumption is 90µW for −22dBm input power and it increases to 800µW for 8.5dBm input power. These performances are beyond the current state-of-the-art.

A 700MHz output bandwidth, 30dB dynamic range, common-base mm-wave power detector

Shielded coplanar waveguides are promising candidates for the development of high quality factor transmission lines in millimeter-wave frequency bands. In this article, state-of-the-art experimental results carried out on a CMOS 0.35 μm low-cost technology are presented. This letter especially deals with the benchmark of slow-wave transmission lines in focusing on the impact of technology dispersion on the measurement results. Eight dies have been measured, each from a different wafer, showing a robust design versus the technology. These results open new possibilities for the development of miniaturized low-loss compact passive devices. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2786–2789, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25598

Jean-Michel Fournier

Papers

Shielded coplanar striplines for RF integrated applications

Efficiency enhancement using adaptive bias control for 60GHz power amplifier

Generic Electrostatic Discharges Protection Solutions for RF and Millimeter-Wave Applications

A 700MHz output bandwidth, 30dB dynamic range, common-base mm-wave power detector

Impact of technology dispersion on slow‐wave high performance shielded CPW transmission lines characteristics