This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters

This work presents and analyzes the design of a 1-V ultra-low power, compact, and wideband low-noise amplifier (LNA). The proposed LNA uses common-gate (CG) NMOS and PMOS transistors as input devices in a complementary current-reuse structure. Low power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor to improve the current efficiency of the LNA. A forward body biasing (FBB) scheme is exploited to tune the feedback coefficient. The complementary characteristics of the input stage leads to partial second-order distortion cancellation. The proposed inductorless LNA is implemented in an IBM 0.13- $\mu {\text {m}}~1$ P8M CMOS technology and occupies only $0.0052~{\text {mm}}^{2}$ . The measured LNA has a 12.3-dB gain 4.9-dB minimum noise figure (NF) input referred third-order intercept point (IIP3) of −10 dBm and 0.1–-2.2 GHz bandwidth (BW), while consuming only 400 $\mu {\text {A}}$ from a 1-V supply.

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

This paper proposes a new microstrip slow-wave structure. The unit cell comprises a Schiffman section of meander line and a shunt open-circuited stub. No via-holes and ground-plane patterns are required. Simple design formulas can be used to obtain line parameters, such as the characteristic impedance and phase velocity. According to the analysis, the characteristic impedance and slow-wave factor of the proposed slow-wave line can be independently controlled by merely two layout parameters. The proposed uniplanar structure only requires a single-layer substrate and is simply constructed using the conventional printed circuit board manufacturing process. A branch-line and a rat-race coupler were designed and fabricated using the proposed structure to demonstrate its feasibility. Their sizes are only 8.49% and 4.87% of the conventional ones, respectively. This novel slow-wave structure should find wide applications in compact microwave circuits.

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A High Slow-Wave Factor Microstrip Structure With Simple Design Formulas and Its Application to Microwave Circuit Design

A fully integrated low-dropout-regulated step-down multiphase-switched-capacitor DC–DC converter (a.k.a. charge pump, CP) with a fast-response adaptive-phase (Fast-RAP) digital controller is designed using a 65-nm CMOS process. Different from conventional designs, a low-dropout regulator (LDO) with an NMOS power stage is used without the need for an additional step-up CP for driving. A clock tripler and a pulse divider are proposed to enable the Fast-RAP control. As the Fast-RAP digital controller is designed to be able to respond faster than the cascaded linear regulator, transient response will not be affected by the adaptive scheme. Thus, light-load efficiency is improved without sacrificing the response time. When the CP operates at 90 MHz with 80.3% CP efficiency, only small ripples would appear on the CP output with the 18-phase interleaving scheme, and be further attenuated at $V_{{\rm OUT}}$ by the 50-mV dropout regulator with only 4.1% efficiency overhead and 6.5% area overhead. The output ripple is less than 2 mV for a load current of 20 mA.

An NMOS-LDO Regulated Switched-Capacitor DC–DC Converter With Fast-Response Adaptive-Phase Digital Control

— This article presents a power detector proposed for low-cost millimeter-wave applications. Thus, the detector uses MOSFET transistor in sub-threshold region in order to realize the signal rectification benefiting from the natural exponential characteristics of MOS transistor in this regime. The detector was designed using the BiCMOS 55 nm technology from ST-Microelectronics. Thanks to this technology, the bipolar version of the detector has also been designed allowing comparison of these two cells. Each of them consume only 30 𝝁� with an 80µm x 80µm area. Theoretical analysis and simulation results demonstrate the advantage of MOS detector in terms of input impedance which reduces the impact of the detector on the device under test (DUT). However, the bipolar detector provides faster responses due to its higher current capability. The MOS based detector has a response time of 1 ns. Its detection range and sensitivity are 20 dB and -18 dBm respectively, in the 50 GHz to 90 GHz frequency band, and are limited by the interconnections parasitic. The design and optimization steps are described in order to provide a general methodology to design high performance power detectors.

Sub-Threshold Based Power Detector for Low-Cost Millimeter-Wave Applications

Advanced CMOS technologies provide an easier way to realize radio-frequency integrated circuits (RFICs). However, transistor gates are getting smaller and electrostatic discharges (ESD) issues become more significant. Unfortunately, ESD protections parasitic capacitance limits the operating bandwidth of the RFICs. ESD protection size dimensions are also an issue to protect RFICs. This paper presents measurements results of ESD protection devices able to be implemented in an I/O pad in advanced CMOS technologies.

Transmission line with 2-kV HBM broadband ESD protection using BIMOS and SCR in advanced CMOS technologies

A fully integrated power management unit for an ultra-low-cost SoC is presented. A multi-stage power management unit is introduced with different power domains controlled by 10 Low Dropout (LDO) regulators. LDOs are designed with NMOS pass-transistors only and without external capacitance output. A 2X charge-pump and a bandgap circuitry supply the reference voltages. The stability of LDO, line and load regulations are achieved using a second fast feedback loop which takes over control at high frequencies. A regulated cascode current-mirror architecture is proposed to filter the switching noise of the chargepump, to drive properly the gate of the pass NMOS and to achieve a PSR higher than -40dB over a wide frequency range. The fully on-chip LDO regulator is able to deliver 1.2V at a loading current of 20mA with a dropout of 100mV. The power management unit can provide 200mA and it consumes only 0.2% of the total battery current. The circuit is designed in a 90nm CMOS process from STMicroelectronics and needs 0.24mm2 silicon area.

Fully integrated power management unit (PMU) using NMOS Low Dropout regulators

This paper presents a V-Band Bi-CMOS 55nm power detector designed to be used in mmWave circuits for automatic level control (ALC) and built-in self test (BIST). The proposed detector shows a simulated detection range of about 35 dB in the 50 GHz to 90 GHz frequency band. Sensitivity to -30 dBm input power is demonstrated thanks to the use of common base bipolar transistor as input stage. The design and optimization steps are described in order to provide a general methodology to design high performance power detectors.

A V-Band BiCMOS power detector for millimeter-wave applications

A low power and high linearity millimeter wave mixer for automotive radar application is designed using SiGe BiCMOS technology. The concept of design is based on a Gilbert type cell. The proposed topology uses separated voltage sources (1.5 V and 2 V for the transconductance and switching stage respectively) via a transformer. This mixer allows high output dynamic range with low power consumption. The chip was characterized by on-wafer measurements. At 77 GHz, the voltage conversion gain (GC) and double side band noise figure (NFDSB) are 13.7 dB and 11.4 dB respectively. Input referred 1-dB compression point (ICP1dB) is 2 dBm. Total power consumption is 15 mW. The size of mixer core is 550 × 410 μm2.

Jean-Michel Fournier

Papers

Sub-Threshold Based Power Detector for Low-Cost Millimeter-Wave Applications

Transmission line with 2-kV HBM broadband ESD protection using BIMOS and SCR in advanced CMOS technologies

Fully integrated power management unit (PMU) using NMOS Low Dropout regulators

A V-Band BiCMOS power detector for millimeter-wave applications

Low power and high linearity millimeter wave differential mixer using passive transformer