This paper presents a complete 0.13 μm SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280 GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2 fF/μm2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors. Details are given on HBT integration, reliability and models as well as on back-end devices models.

0.13 $\mu$ m SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices.

High-Performance Shielded Coplanar Waveguides for the Design of CMOS 60-GHz Bandpass Filters

This paper reports the design and analysis of 21-29-GHz CMOS low-noise amplifier (LNA), balun and mixer in a standard 0.18-μm CMOS process for ultra-wideband automotive radar systems. To verify the proposed LNA, balun, and mixer architectures, a simplified receiver front-end comprising an LNA, a double-balanced Gilbert-cell-based mixer, and two Marchand baluns was implemented. The wideband Marchand baluns can convert the single RF and local oscillator (LO) signals to nearly perfect differential signals over the 21-29-GHz band. The performance of the mixer is improved with the current-bleeding technique and a parallel resonant inductor at the differential outputs of the RF transconductance stage. Over the 21-29-GHz band, the receiver front-end exhibits excellent noise figure of 4.6±0.5 dB, conversion gain of 23.7±1.4 dB, RF port reflection coefficient lower than -8.8 dB, LO-IF isolation lower than -47 dB, LO-RF isolation lower than -55 dB, and RF-IF isolation lower than -35.5 dB. The circuit occupies a chip area of 1.25×1.06 mm2, including the test pads. The dc power dissipation is only 39.2 mW.

Design and Analysis of a 21–29-GHz Ultra-Wideband Receiver Front-End in 0.18- $\mu$ m CMOS Technology

This paper presents a complete 0.13 mum SiGe BiCMOS technology fully dedicated to millimeter-wave applications, including a high-speed (230/280GHz fT/fMAX) and medium voltage SiGe HBT, thick-copper back-end designed for high performance transmission lines and inductors, 2fF/mum2 high-linearity MIM capacitor and complementary double gate oxide MOS transistors.

0.13μm SiGe BiCMOS technology for mm-wave applications

The overall purpose of this paper is the prediction of the ultimate electrical high-frequency performance potential for SiGeC HBTs under the constraints of practical applications. This goal is achieved by utilizing advanced device simulation tools with parameters calibrated to experimental results of most advanced existing technologies. In addition, detailed electrostatic and electrothermal simulations are performed for determining the parasitic capacitances, temperature increase, and safe operating area of aggressively scaled devices. The important figures of merit are then determined from circuit simulation employing an accurate compact model incorporating all relevant physical effects. Based on the vertical profile found in Part I, this paper focuses on achieving a balanced device design by lateral scaling. It is shown that the peak values of (fT, fmax) around (1, 1.5) THz may be achievable. Such a performance limit provides still significant headroom for further developing existing processes and makes SiGeC HBTs well-suitable for highly integrated millimeter-wave applications operating within the low-end of the terahertz gap.

Physical and Electrical Performance Limits of High-Speed Si GeC HBTs—Part II: Lateral Scaling

The effects of RF hot-carrier stress on the characteristics of 60-GHz power amplifiers (PAs) on a CMOS 65-nm process are investigated, for the first time, in this letter. A reliability study is made on a one-stage PA to validate an aging model and the degradation explanation. A drop of 16% of the gain, 17% of the 1-dB output compression point (OCP1 dB), and 17% of the Psat are measured at 60 GHz after 50 h of stress under Vdd = 1.65 V with Pin = 0 dBm and Vdd = 1.9 V with Pin = -10 dBm at 60-GHz frequency.

Hot-Carrier Stress Effect on a CMOS 65-nm 60-GHz One-Stage Power Amplifier

An improved analytical model of the CMOS 65-, 45-, and 32-nm silicon technology integrated transmission line is proposed. This model is derived from previous classical ones used for printed circuits board lines. Improvements have been performed to take into account the size of integrated lines. The study is validated up to millimeter-wave frequencies for different linewidths realized with various metal levels. Accurate results allow the model to be implemented in commercial computer-aided design software commonly used for millimeter-wave designs. A comparison with commercial tools is carried out.

65-, 45-, and 32-nm Aluminium and Copper Transmission-Line Model at Millimeter-Wave Frequencies

A fully integrated single-pole double-throw (SPDT) transmit/receive switch (T/R switch) is implemented on a standard 45nm CMOS process. This circuit is dedicated to fully integrated CMOS RF front end modules operating at 94 GHz. The traveling-wave topology was used to minimize the insertion loss at millimeter wave frequencies. The switch exhibits a measured insertion loss of 5.3 dB, an isolation of 20.5 dB, and a return loss at Tx/Rx port of −12 dB at 94 GHz. An input 1dB compression point higher than 11 dBm is measured at 60 GHz and 15 dBm at 94 GHz after simulation. Excellent agreement between measurement and simulation results is observed.

A SPDT switch in a standard 45 nm CMOS process for 94 GHz Applications

A millimeter-wave Power Amplifier (PA) implemented in a 65nm CMOS process with 8-metal layers and transistor f T /f MAX of 160/200 GHz is reported. The PA operates from a 1.2V supply voltage. A power gain of 13.4 dB, an output P1dB of 12.2 dBm with 7.6 % PAE and a saturated output power of 13.8 dBm at 58 GHz are measured. S 11 and S 22 are lower than 10 dB, which ensures an input and output matching to a 50 Ω impedance. These results are obtained thanks to accurate millimeter wave models for MOS and integrated microstrip lines used as passive components. The amplifier design takes electromigration constraints at 105°C into account. Excellent agreement between measurement and simulation results is observed.

A CMOS class-A 65nm power amplifier for 60 GHz applications

A hot carrier ageing model previously validated on a one-stage 60-GHz power amplifier (PA) is demonstrated to be able to predict the degradation of the characteristic parameters for multistage high-performance millimeter-wave (mmW) PAs. The increase in the threshold voltage, the decrease in the transconductance, and the output conductance of the MOSFETs caused by hot carriers leads to a degradation in performance of the PAs. Consequently, by using this ageing model, the mmW PA lifetime can be extracted. A new PA is then designed, taking into account the ageing effects, and is shown to be reliable during ten years. This amplifier exhibits a power gain of 20 dB, an output 1-dB compression point of 12.5 dBm with 6.6% power-added efficiency, and a saturated output power of 16 dBm at 60 GHz.

L. Moquillon

Papers

Hot-Carrier Stress Effect on a CMOS 65-nm 60-GHz One-Stage Power Amplifier

65-, 45-, and 32-nm Aluminium and Copper Transmission-Line Model at Millimeter-Wave Frequencies

A SPDT switch in a standard 45 nm CMOS process for 94 GHz Applications

A CMOS class-A 65nm power amplifier for 60 GHz applications

Design-in-Reliable Millimeter-Wave Power Amplifiers in a 65-nm CMOS Process