In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.

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CMP network-on-chip overlaid with multi-band RF-interconnect

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

A low Terahertz (324 GHz) frequency generator is realized in 90 nm CMOS by linearly superimposing quadruple (N=4) phase shifted fundamental signals at one fourth of the output frequency (81 GHz). The developed technique minimizes the fundamental, second and third order harmonics without extra filtering and results in a high fundamental-to-4 th harmonic signal conversion ratio of 0.17 or -15.4 dB. The demonstrated prototype produces a calibrated -46 dBm output power when biased at 1 V and 12 mA with 4 GHz tuning range and extrapolated phase noise of -91 dBc/Hz at 10 MHz frequency offset. The linear superposition (LS) technique can be generalized for all even number cases (N=2k, where k=1,2,3,4,...,n) with different tradeoffs in output power and frequency. As CMOS continues to scale, we anticipate the LS N=4 VCO to generate signals beyond 2 Terahertz by using 22 nm CMOS and produce output power up to -1.5 dBm with 1.7% power added efficiency with an LS VCO + Class-B Power Amplifier cascaded circuit architecture.

Terahertz CMOS Frequency Generator Using Linear Superposition Technique

A novel millimeter-wave Intra-Connect solution for short range, high speed, internal I/O connections in low-power logic 40 nm CMOS process is demonstrated. The system consists of a transmitter and a receiver that uses binary amplitude shift keying (ASK) modulation for a compact and power efficient design. The receiver realizes coherent demodulation using injection locking without a PLL or an external reference clock utilizing a path to inject the received signal into the VCO. The demonstrator achieves 11 Gb/s ASK data transmission over 14 mm using bond-wire antennas with a bit error rate (BER) of less than 10-11. The active footprint of the transmitter is 0.06 mm2 and the power consumption is 29 mW with an energy usage of 6.4 pj/bit per channel. The receiver occupies the active footprint of 0.07 mm2 and consumes 41 mW. The work shows the feasibility of the millimeter-wave Intra-Connect for high speed internal I/O connections.

A millimeter-wave intra-connect solution

Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Methods and systems for computer aided design of 3D integrated circuits

Future inter- and intra-ULSI interconnect systems demand extremely high data rates (up to 100 Gbps/pin or 20-Tbps aggregate) as well as bidirectional multiI/O concurrent service, re-configurable computing/processing architecture, and total compatibility with mainstream silicon system-on-chip and system-in-package technologies. In this paper, we review recent advances in interconnect schemes that promise to meet all of the above system requirements. Unlike traditional wired interconnects based solely on time-division multiple access for data transmission, these new interconnect schemes facilitate the use of additional multiple access techniques including code-division multiple access and frequency-division multiple access to greatly increase bandwidth and channel concurrency as well as to reduce channel latency. The physical transmission line is no longer limited to a direct-coupled metal wire. Rather, it can be accomplished via either wired or wireless mediums through capacitor couplers that reduce the baseband noise and dc power consumption while simplifying the fabrication process by eliminating vertical metal studs needed in three-dimensional ICs. These new advances in interconnect schemes would fundamentally alter the paradigm of ULSI data communications and enable the design of next-generation computing/processing systems.

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Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications

Two RF techniques are combined with capacitive coupling interconnect to form ultra-wide-bandwidth impulse interconnect and RF interconnect in 3D IC technology. They achieve 10Gb/s/pin and 11Gb/s/pin transmission with 2.7mW/pin and 4.35mW/pin power consumption, respectively, using the MIT Lincoln Lab 3D 0.18mum CMOS, an 8times improvement over previous work

Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs

An RF/baseband FDMA-interconnect transceiver, implemented in 0.18 /spl mu/m CMOS, enables reconfigurability and multiple access for multi-I/Os on a shared bus. The RF/baseband transceiver achieves an aggregate data rate of 3 Gb/s/pin (3.6 Gb/s/pin) for bi-directional (uni-directional) signaling while dissipating 92 mW and occupying 0.65 mm/sup 2/.

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

A Self-Synchronized Radio Frequency RF-Interconnect (SSRFI), based on capacitor coupling and peak detection, for vertically interconnecting active device layers in three-dimensional (3D) integrated circuits (IC), as well as wireless communication and RF signal transmission/receiving.

Self-synchronized radio frequency interconnect for three-dimensional circuit integration

A self-synchronized RF-interconnect (SSRFI), based on capacitive coupling and peak signal detection, is presented. In this SSRFI, small coupling capacitor (60fF) is used to interconnect vertical active layers in 3-Dimensional IC. The demonstrated SSRFI system, including both transmitter and receiver, has been designed, fabricated and verified in UMC 0.18 /spl mu/m CMOS with a PRBS data rate of 3Gbit/s, a BER of 1.2/spl times/10/sup -10/ and a rms jitter of 1.28ps. The core circuit burns 4mW from a 1.8V supply and occupies 0.02mm/sup 2/ chip area.

Jenwei Ko

Papers

Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications

Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

Self-synchronized radio frequency interconnect for three-dimensional circuit integration

Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling