In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.

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CMP network-on-chip overlaid with multi-band RF-interconnect

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

An integrated circuit transmission system includes a dielectric substrate wave guide and first and second substrate antennas A substrate transmitter is operable to produce an radio frequency (RF) signal, the RF signal having first and second components A micro-strip resonator filter module generates a filtered RF signal by adjusting phases of the first and second components of the RF signal via selection of one of a plurality of selectable tap points A third substrate antenna generates a beam formed signal for transmission through the dielectric substrate wave guide, wherein the beam form signal is directed, via the filtered RF signal, to either the first substrate antenna or the second substrate antenna

High frequency signal combining

We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-mum silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1Hz-15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration

Capacitive Inter-Chip Data and Power Transfer for 3-D VLSI

Methods and systems for generating and verifying circuit layouts from computer-aided design tools for vertically integrated, three-dimensional integrated circuits are disclosed. In one instance, a 3-D technology file of these teachings is obtained by providing an identifier for two or more circuit levels, providing for each one of the two or more circuit levels an identifier for a 2-D technology file corresponding to each of the one or more circuit levels and providing a file structure including the two or more circuit levels and each identifier, corresponding to each one of the one or more circuit levels, for the 2-D technology file corresponding to each one of the two or more circuit levels. Other embodiments are disclosed.

Methods and systems for computer aided design of 3D integrated circuits

Future inter- and intra-ULSI interconnect systems demand extremely high data rates (up to 100 Gbps/pin or 20-Tbps aggregate) as well as bidirectional multiI/O concurrent service, re-configurable computing/processing architecture, and total compatibility with mainstream silicon system-on-chip and system-in-package technologies. In this paper, we review recent advances in interconnect schemes that promise to meet all of the above system requirements. Unlike traditional wired interconnects based solely on time-division multiple access for data transmission, these new interconnect schemes facilitate the use of additional multiple access techniques including code-division multiple access and frequency-division multiple access to greatly increase bandwidth and channel concurrency as well as to reduce channel latency. The physical transmission line is no longer limited to a direct-coupled metal wire. Rather, it can be accomplished via either wired or wireless mediums through capacitor couplers that reduce the baseband noise and dc power consumption while simplifying the fabrication process by eliminating vertical metal studs needed in three-dimensional ICs. These new advances in interconnect schemes would fundamentally alter the paradigm of ULSI data communications and enable the design of next-generation computing/processing systems.

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Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications

A fully-integrated 8.4 Gb/s 2.5 pJ/b mobile memory I/O transceiver using simultaneous bidirectionaldual band signaling is presented. Incorporating both RF-band and baseband transceiver designs, this prototype demonstrates an energy-efficient and high-bandwidth solution for future mobile memory I/O interface. The proposed amplitude shift keying (ASK) modulator/demodulator with on-chip band-selective transformer obviates a power hungry pre-emphasis and equalization circuitry, revealing a low-power, compact and standard mobile memory-compatible solution. Designed and fabricated in 65-nm CMOS technology, each RF-band and baseband transceiver consumes 10.5 mW and 11 mW and occupies 0.08 mm2 and 0.06 mm2 die area, respectively. The dual-band transceiver achieves error-free operation (BER <; 10-15 ) with 223- 1 PRBS at 8.4 Gb/s over a distance of 10 cm.

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling

The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication bandwidth and concurrency of small-scale digital systems. To improve the overall system performance without increasing communication resources and complexity, this paper presents a cost-effective interconnect architecture, communication protocol, and signaling technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SSCDMA-I) enables dual concurrent transactions on a single wire line as well as flexible input/output (I/O) reconfiguration. The SSCDMA-I utilizes 2-bit orthogonal CDMA coding and a variation of source synchronous clocking for multilevel superposition; a single 3-level SSCDMA-I line operates as if it consists of dual virtual time-multiplexed interconnects, which exploits communication parallelism with a reduced number of pins, wires, and complexity. The unique multiple access capability of the SSCDMA-I improves real-time communication between multiple semiconductor intellectual property (IP) blocks on a shared link or bus by reducing the bus contention interference from simultaneous traffic requests and by taking advantage of shorter request latency. The prototype transceiver chip is implemented in 0.18-m CMOS and the 10-cm test PC board system achieves an aggregate data rate of 2.5 Gb/s/pin between four off-chip (2Tx-to-2Rx) I/Os.

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Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

An RF/baseband FDMA-interconnect transceiver, implemented in 0.18 /spl mu/m CMOS, enables reconfigurability and multiple access for multi-I/Os on a shared bus. The RF/baseband transceiver achieves an aggregate data rate of 3 Gb/s/pin (3.6 Gb/s/pin) for bi-directional (uni-directional) signaling while dissipating 92 mW and occupying 0.65 mm/sup 2/.

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

A temperature condition indicator in a fabricated integrated circuit provides first and second voltage signals that vary with the temperature of the fabricated integrated circuit. The first voltage signal increases as the temperature of the fabricated integrated circuit increases and decreases as the temperature of the fabricated integrated circuit decreases. The second voltage signal decreases as the temperature of the fabricated integrated circuit increases and increases as the temperature of the fabricated integrated circuit decreases. The first and second voltage signals are about equal (or intersect) when the temperature of the fabricated integrated circuit is about equal to a first temperature. The first temperature is selected to correspond to a temperature out of range condition. The intersection of the first and second voltage signals may thereby indicate a threshold temperature for the operation of the fabricated integrated circuit. If a first temperature out of range condition occurs at about T degrees, the first and second voltage signals are controlled so that the intersection of the first and second voltage signals is about equal to a voltage level that corresponds to about the threshold temperature. The levels of the first and second voltage signals can be shifted to adjust the intersection of the first and second voltage signals so that the threshold temperature can be adjusted.

Jongsun Kim

Papers

Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications

An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

Devices for controlling temperature indications in integrated circuits using adjustable threshold temperatures