In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of area overhead on the active layer, RF-I can provide an average 13% (max 18%) boost in application performance, corresponding to an average 22% (max 24%) reduction in packet latency. We observe that RF access points may become traffic bottlenecks when many packets try to use the RF at once, and conclude by proposing strategies that adapt RF-I utilization at runtime to actively combat this congestion.

/pdf/cmp-network-on-chip-overlaid-with-multi-band-rf-interconnect-31zf9206vc.pdf

CMP network-on-chip overlaid with multi-band RF-interconnect

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. 

This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.

KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

On-Chip Communication Architectures: System on Chip Interconnect

The contributions of integrated circuits to the RF front-end of wireless receivers and transmitters operating in broadcast and personal communications bands are surveyed. It is seen from this that when ICs enable a rethinking of the RF architecture, the wireless device can sometimes become significantly smaller, and consume much less power. Examples are taken from FM broadcast receivers, pagers, and cellular telephone handsets. Many semiconductor technologies are competing today to supply RF-ICs to cellular telephones. The various design styles and levels of integration are compared, with the conclusion that single-chip silicon transceivers, combined with architectures which substantially reduce off-chip passive components, will likely dominate digital cellular telephones in the near future. The survey also projects future trends for ICs for miniature spread-spectrum transceivers offering robust operation in the crowded spectrum. With sophistication in baseband digital signal processing, its increasing interaction with the RF sections, and with increasing experience in simplified radio architectures, all-CMOS radios appear promising in the 900 MHz to 2 GHz bands. A specific CMOS spread-spectrum transceiver project underway at the author's institution is discussed by way of example. >

Low-power radio-frequency ICs for portable communications

The authors consider a networking environment in which the users are mobile, the topology changes, code division multiple access (CDMA) provides multiple wireless channels, the bandwidth of a given link is unpredictable and possibly very low, the error rates are extremely high and variable, major interference occurs when multiple transmissions take place over (possibly different) links on the same or different codes, real-time multimedia traffic must be supported as well as datagram traffic, there is no stable communication infrastructure, and there is no central control. They consider the problem of developing a design prototyping methodology, performance evaluation techniques, and networking algorithms to support a rapidly deployable radio network for such an environment. The network must be capable of providing guaranteed quality of service (QoS) to real-time multimedia traffic in a mobile, wireless, multihop radio network with no fixed infrastructure (e.g., no base stations). Another element of the environment with which they deal is that of multihop communications. They focus on two layers of key importance in multimedia wireless network design, namely compression algorithms and adaptivity in the voice/video applications layer, and network algorithms at the wireless subnet layer. Simulation tools are used to evaluate our design as well as to provide a path toward their implementation in software.

adaptive mobile multimedia networks

The contributions of integrated circuits to the RF front-end of wireless receivers and transmitters operating in broadcast and personnal communications bands are surveyed. It is seen from this that when 1C's enable a rethinking of the RF architecture, the wireless device can sometimes become significantly smaller, and consume much less power. Examples are taken from FM broadcast receiver, pagers, and cellular telephone handsets. Many semiconductor technologies are competing today to supply RF-1C's to cellular telephones. The various design styles and levels of integration are compared, with the conclusion that single-chip silicon transceivers, combined with architectures which substantially reduce off-chip passive components, will likely dominate digital cellular telephones in the near future. The survey also projects future trends for 1C's for miniature spread-spectrum transceivers offering robust operation in the crowded spectrum. With sophistication in baseband digital signal processing, its increasing interaction with the RF sections, and with increasing experience in simolified radio architectures, all-CMOS radios appear promising in the 900 MH z to 2 GH z bands. A specific CMOS spread-spectrum transceiver project underway at the author's institution is discussed by way of example

Low-power radio-frequency IC's for portable communications

Future inter- and intra-ULSI interconnect systems demand extremely high data rates (up to 100 Gbps/pin or 20-Tbps aggregate) as well as bidirectional multiI/O concurrent service, re-configurable computing/processing architecture, and total compatibility with mainstream silicon system-on-chip and system-in-package technologies. In this paper, we review recent advances in interconnect schemes that promise to meet all of the above system requirements. Unlike traditional wired interconnects based solely on time-division multiple access for data transmission, these new interconnect schemes facilitate the use of additional multiple access techniques including code-division multiple access and frequency-division multiple access to greatly increase bandwidth and channel concurrency as well as to reduce channel latency. The physical transmission line is no longer limited to a direct-coupled metal wire. Rather, it can be accomplished via either wired or wireless mediums through capacitor couplers that reduce the baseband noise and dc power consumption while simplifying the fabrication process by eliminating vertical metal studs needed in three-dimensional ICs. These new advances in interconnect schemes would fundamentally alter the paradigm of ULSI data communications and enable the design of next-generation computing/processing systems.

/pdf/advanced-rf-baseband-interconnect-schemes-for-inter-and-57ozn0i75t.pdf

Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications

An RF/baseband FDMA-interconnect transceiver, implemented in 0.18 /spl mu/m CMOS, enables reconfigurability and multiple access for multi-I/Os on a shared bus. The RF/baseband transceiver achieves an aggregate data rate of 3 Gb/s/pin (3.6 Gb/s/pin) for bi-directional (uni-directional) signaling while dissipating 92 mW and occupying 0.65 mm/sup 2/.

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

This paper describes a fully integrated digital-spread spectrum transceiver chip fabricated through MOSIS in 1.2 /spl mu/m CMOS. It includes a baseband spread spectrum transmitter and a coherent intermediate frequency (IF) receiver consisting of a Costas loop, an acquisition loop for the pseudo-noise (PN) sequence, and a clock recovery loop with a 406.4 MHz onchip numerically controlled oscillator (NCO). The transceiver is capable of operating at a maximum IF sampling rate of 50.8 MS/s and a maximum chip rate of 12.7 R Mchips/s (Mcps) with selectable data rates of 100, 200, 400, and 800 kbps. At the maximum operating speed of 50.8 R MS/s, it dissipates 1.1 W. In an additive white Gaussian noise channel the IF receiver achieves a receiver output SNR within 1 dB of theory and can acquire code with a wide range of input SNR from -17 dB to over 30 dB. The transceiver chip has been interfaced to an RF up/down converter to demonstrate a wireless voice/data/video link operating in the 902-928 MHz band. >

A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 /spl mu/m CMOS

A 2.7 Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18 /spl mu/m CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8 ns. The chip-set dissipates 74 mW and occupies 0.3 mm/sup 2/ per I/O pair.

A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

Spread spectrum transmission, with its code division multiple access capability, meets the stringent requirements in high-capacity wireless communication systems that must also be robust to multipath fading. A key component in the spread-spectrum radio is the transceiver. For integration into portable products such as notebook computers, it is desirable to have an integrated single-chip transceiver. The SSRX chip receiver presented in this paper is designed for low SNR loss by using a coherent architecture, allowing applications ranging from voice to data transmission. The three components in the coherent architecture are the Costas loop, the PN-acquisition loop, and the clock recovery loop. To maintain system stability, the loop bandwidths are chosen through simulation and each loop is isolated from the others during acquisition through a control sequence provided by a finite-state machine. >

http://ieeexplore.ieee.org/iel2/1111/8026/00344741.pdf

C. Chien

Papers

Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications

An RF/baseband FDMA-interconnect transceiver for reconfigurable multiple access chip-to-chip communication

A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 /spl mu/m CMOS

A 2.7 Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

A 12.7 Mchip/s all-digital BPSK direct sequence spread-spectrum IF transceiver in 1.2 /spl mu/m CMOS