In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance ( ${R}_{\text {sp,on}}$ ). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge ( ${Q}_{g}$ ) and miller capacitance ( ${c}_{\text {rss}}$ ) compared to SJ MOSFET.

Design and Optimization of SiC Super-Junction MOSFET Using Vertical Variation Doping Profile

Owing to the superior properties of silicon carbide (SiC), such as higher breakdown voltage, higher thermal conductivity, higher operating frequency, higher operating temperature, and higher saturation drift velocity, SiC has attracted much attention from researchers and the industry for decades. With the advances in material science and processing technology, many power applications such as new smart energy vehicles, power converters, inverters, and power supplies are being realized using SiC power devices. In particular, SiC MOSFETs are generally chosen to be used as a power device due to their ability to achieve lower on-resistance, reduced switching losses, and high switching speeds than the silicon counterpart and have been commercialized extensively in recent years. A general review of the critical processing steps for manufacturing SiC MOSFETs, types of SiC MOSFETs, and power applications based on SiC power devices are covered in this paper. Additionally, the reliability issues of SiC power MOSFET are also briefly summarized.

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Review of Silicon Carbide Processing for Power MOSFET

Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.

Power semiconductor devices, structures, and related methods

A novel superjunction (SJ) lateral double-diffused MOSFET (LDMOS) with a deep High- K (HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations. The HK dielectric trench is embedded under the n+ drain, which is connected with the drain electrode. In the OFF-state, the reshaping effect of HK trench enhances the bulk electric field strength and weakens the peak electric field around the edge of the drain diffusion, which increases the breakdown voltage (BV). Moreover, because of the assistant depletion effect by the HK trench, a lower resistivity substrate is allowed for HK SJ-LDMOS, which also increases the doping concentration of the n-type buffer layer under the SJ layer of HK SJ-LDMOS, correspondingly. Thus, a lower specific ON-resistance ( ${R}_{ \mathrm{ ON},\text {sp}}$ ) is also obtained. Simulation results show that the BV increases by 35.2% in comparison with the conventional buffered SJ-LDMOS with the same drift length. Moreover, HK SJ-LDMOS presents an excellent figure of merit, which is two times higher than that of the conventional buffered SJ-LDMOS.

Novel Superjunction LDMOS With a High- K Dielectric Trench by TCAD Simulation Study

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side ( ${T}_{\textit {E}})$ and near the collector side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

Superjunction has arguably been the most creative and important concept in power device field Superjunction vertical diffused MOSFET (SJ VDMOS) has been commercialized and the research effort to l

A Review of Superjunction Vertical Diffused MOSFET

This paper proposes a U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to reduce the turn-off loss while keep the low ON-state voltage drop. The device features a U-shaped gate trench (G1) and a U-shaped hole-barrier trench (G2). By introducing the dual trenches, enhanced carrier stored effect at the emitter side, more uniform carrier distribution in the drift region, and low carrier density at the collector are realized, resulting in decreases of ON-state voltage drop ( ${V}_{\mathrm{\scriptscriptstyle ON}}$ ) and turn-OFF loss ( ${E}_{\mathrm{\scriptscriptstyle OFF}})$ . The proposed SOI-LIGBT offers an ${E}_{\mathrm{\scriptscriptstyle OFF}}~52.3$ % lower than the conventional planar-gate U-shaped channel SOI-LIGBT at the same ${V}_{\mathrm{\scriptscriptstyle ON}}$ of 1.22 V. Moreover, the proposed SOI-LIGBT exhibits a latch-up free characteristic at the current density larger than 1200 A/cm2.

A U-Shaped Channel SOI-LIGBT With Dual Trenches

A novel composite device structure named self-adjust conductivity modulation lateral insulated gate bipolar transistor (SCM-LIGBT), including normal LIGBT region (NLT region), the EM-nMOS region (ENM region), and the series diode region (DIO region), is proposed in this paper. By adding the enhanced-mode nMOS region and the series diodes region, the parasitic NPN transistor (NPN) bipolar structure in the normal LIGBT structure can be triggered in on-state and the conductivity modulation is dramatically enhanced, which leads to the improvement on the current capability and the forward voltage. In addition, due to the base voltage of the parasitic NPN bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe operating area. Numerous simulations and measurements are presented to investigate the electrical characteristics of the proposed structure. The length of the fabrication SCM-LIGBT is $78.5~\mu \text{m}$ , and the width of the DIO and NLT is 830 $\mu \text{m}$ , while the width of the ENM is $4100~\mu \text{m}$ . The results demonstrate that the proposed SCM-LIGBT achieves a high-current capability ( ${J}_{A})$ of 2428 A/cm2 at ${V}_{G}= 10$ V, a low on-state voltage drop of 1.15 V at ${J}_{A}= 150$ A/cm2 with its breakdown voltage of 590 V.

Investigation on Self-Adjust Conductivity Modulation SOI-LIGBT Structure (SCM-LIGBT) for Monolithic High-Voltage IC

An anti-noise-interference high-voltage side gate driving circuit comprises a high-voltage level shifting circuit, an RS latch and a driver, the high-voltage level shifting circuit converts the two input low-voltage pulse signals into two high-voltage pulse signals to be output, the two high-voltage pulse signals are respectively processed and then enter the RS latch, the RS latch outputs the signals into the driver, and the driver outputs a driving signal to control an external power tube be to switched on and off. According to the anti-noise-interference high-voltage side gate driving circuit, the high-voltage level shifting circuit is improved, the improved high-voltage level shifting circuit comprises two completely-same independent parts, and each independent part comprises two LDMOSs, a delay unit, a Zener voltage regulator tube, a capacitor, a resistor and a middle-voltage PMOS. The circuit can remove d(i)V(/i)/dt interference noise and differential mode noise, the transmission of normal signals is not affected while the noise interference is removed, and meanwhile the allowable negative VS voltages are increased.

Jian Chen

Papers

A Review of Superjunction Vertical Diffused MOSFET

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

A U-Shaped Channel SOI-LIGBT With Dual Trenches

Investigation on Self-Adjust Conductivity Modulation SOI-LIGBT Structure (SCM-LIGBT) for Monolithic High-Voltage IC

Anti-noise-interference high-voltage side gate driving circuit