A novel 600-V snapback-free and low-loss shorted-anode (SA) silicon on insulator lateral insulated gate bipolar transistor (LIGBT) with self-adaptive resistance (SAR) in anode is proposed and investigated by simulation, named SAR LIGBT. The device is characterized by dual anode trenches which are filled with p-type polysilicon and surrounded by oxide, and the dual trenches are shorted with the anode electrode, separated by the low-doped N− region and N+ anode region. At low anode voltage ( $V_{A}$ ), the N− region is fully depleted by p-type polysilicon, serving as a large resistance to hinder electrons flowing into the N+ anode; at high VA, an electron accumulation layer is formed along the anode trenches to provide a low-resistance path for electron current. Consequently, N− region makes the distributed resistances at the anode side ( ${R}_{\text {SA}}$ ) act as a SAR. It not only eliminates the snapback effect but also reduces on-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off energy loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). Therefore, SAR LIGBT achieves a better tradeoff between $V_{ \mathrm{\scriptscriptstyle ON}}$ and ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ . At the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ , the SAR LIGBT reduces the ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 20.6%, 28.1%, and 30.5% compared with those of multisegment anode, segmented trenches in the anode, and SA-NPN LIGBTs, respectively. Moreover, the SAR LIGBT exhibits the lowest ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 1.71 V and the shortest switching time of 93 ns at $J_{A} = {100}$ A/cm2. In addition, the SAR LIGBT achieves snapback-free with smaller cell pitch than that of separated SA LIGBT.

A Snapback-Free and Low-Loss Shorted-Anode SOI LIGBT With Self-Adaptive Resistance

In this article, a novel reverse-conducting lateral insulated gate bipolar transistor (RC-LIGBT) with embedded diode and p-type Schottky Barrier Diode (p-SBD) is proposed. The two diodes are connected in series through a floating electrode, which provides a current path for carriers in reverse-conducting mode. Compared with the Separated Shorted-Anode RCLIGBT (SSA-RC-LIGBT), the proposed structure not only eliminates the snapback voltage ( $\Delta {V}_{\text {SB}}$ ) but also avoids the waste of device area. Therefore, the superior reverse recovery characteristics and excellent tradeoff relationship between ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ) are obtained. The reverse recovery charge of the proposed RC-LIGBT shows 43.9% and 63.2% reduction compared with those of the SSA-RC-LIGBT with ${L}_{\text {B}}$ (distance between the p+ collector and the shorted n+ collector) being 34 and $64~\mu \text{m}$ , respectively. The turn-off loss of the proposed RC-LIGBT at ${V}_{ \mathrm{\scriptscriptstyle ON}} = {2.6}$ V is reduced by 68.2% and 87.1% compared with those of the SSA-RC-LIGBT with $\sf \Delta {V}_{\text {SB}} = {0.48}$ V and $\sf \Delta {V}_{\text {SB}} = {0.17}$ V, respectively. Moreover, the proposed RC-LIGBT has a self-adjusted collector injection efficiency under different temperatures to dramatically improve the Short Circuit Safe Operation Area (SCSOA).

Simulation Study of a Novel Snapback Free Reverse-Conducting SOI-LIGBT With Embedded P-Type Schottky Barrier Diode

A novel 500 V reverse-conducting (RC) silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual embedded diodes (DEDs) is proposed to eliminate the snapback, and its mechanism is investigated by simulation. The RC is realized by the internal diode, which consists of two p-i-n diodes (D1 and D2). The two diodes are connected in series. In the RC-state, the current flows through D1 first and then through D2. D2 is embedded in the anode region of the proposed DED-LIGBT and is fully isolated by the deep-oxide trench. In the forward conducting state, D2 is reverse biased and the electrons from the N+ cathode can only flow into the P+ anode. The DEDs reroute the electron current path, and thus, the snapback is avoided. Moreover, by adjusting the width of D2 ( ${W}_{b})$ , the internal diode of the DED structure achieves superior reverse recovery time ( ${t}_{\text {rr}})$ and reverse recovery peak current ( ${I}_{\text {rrm}})$ to the conventional SOI p-i-n diode.

Novel Snapback-Free Reverse-Conducting SOI-LIGBT With Dual Embedded Diodes

A new 600V SOI shorted-anode LIGBT with multi-segment anode (MSA) is proposed and investigated in this paper. The device features a multi-segmented P+ anode and p-buried layers (PBL) formed in both anode and cathode regions. The combination of MSA and the PBL below the anode increase the anode distributed resistance (R sa ) and effectively suppress snapback effect with small dimensions in both x- and z-directions. The PBL below cathode n+ serves as a low-resistance bypass for on-state hole current and is conducive to latch-up immunity. A compact analytical model is further presented to evaluate the impact of key parameters of the MSA on the snapback voltage (V sb ). Simulation shows that the MSA LIGBT achieves the V sb off ), the MSA LIGBT reduces the on-state voltage (F on ) by 50% compared to the separated shorted anode (SSA) LIGBT. The MSA LIGBT exhibits no latch-up issue at the high voltage and high current up to 1600A/cm2. The short circuit withstand time of the proposed structure achieves 6X improvement compared to that of the conventional LIGBT.

A snapback-free shorted-anode SOI LIGHT with multi-segment anode

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side ( ${T}_{\textit {E}})$ and near the collector side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

This paper presents the electrical characteristic of a 500 V silicon-on-insulator (SOI) lateral insulated-gate bipolar transistor (LIGBT) with segmented trenches in the anode (STA) region. The STA-LIGBT features segmented n+ anodes and segmented trenches. The segmented n+ anodes are shorted to the p+ anode, which accelerates the extraction of stored electrons during the device turn-OFF. The segmented trenches are arranged between the p+ anode and the shorted n+ anode. The resistors between the adjacent segmented trenches and the adjacent segmented n+ anodes contribute to low snapback voltage ( $V_{S}$ ) while maintain high current density. In addition, an internal diode is formed by introducing the shorted n+ anode. The 3-D simulations and the experiments are carried out to characterize the electrical performances of the STA-LIGBT and its internal diode. Compared with the conventional SOI-LIGBT, the STA device achieves a 73% improvement in turn-OFF time ( $t_{\mathrm{\scriptscriptstyle OFF}}$ ) at the same current density. Correspondingly, the internal diode of the STA-LIGBT achieves a forward voltage drop ( $V_{F}$ ) of 1.32 V and a reverse recovery time ( $t_{\mathrm {rr}}$ ) of 321 ns, which are superior to those of a conventional p-i-n SOI diode.

Electrical Characteristic Study of an SOI-LIGBT With Segmented Trenches in the Anode Region

This paper proposes a U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to reduce the turn-off loss while keep the low ON-state voltage drop. The device features a U-shaped gate trench (G1) and a U-shaped hole-barrier trench (G2). By introducing the dual trenches, enhanced carrier stored effect at the emitter side, more uniform carrier distribution in the drift region, and low carrier density at the collector are realized, resulting in decreases of ON-state voltage drop ( ${V}_{\mathrm{\scriptscriptstyle ON}}$ ) and turn-OFF loss ( ${E}_{\mathrm{\scriptscriptstyle OFF}})$ . The proposed SOI-LIGBT offers an ${E}_{\mathrm{\scriptscriptstyle OFF}}~52.3$ % lower than the conventional planar-gate U-shaped channel SOI-LIGBT at the same ${V}_{\mathrm{\scriptscriptstyle ON}}$ of 1.22 V. Moreover, the proposed SOI-LIGBT exhibits a latch-up free characteristic at the current density larger than 1200 A/cm2.

A U-Shaped Channel SOI-LIGBT With Dual Trenches

In this paper, the clamped inductive turn-off failure of the Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) with multiple fingers under high-voltage and high-current conditions is investigated. First, the measured turn-off waveforms combining with the on-state I-V characteristics of the failed device are discussed to distinguish the probable cause of the failure. Then, two-dimensional (2-D) electrothermal simulations are performed to reproduce the failure by using Sentaurus TCAD. The failure is originated from an inhomogeneous depletion behavior among the paralleled fingers during the turn-off, which gives rise to the non-uniform current-sharing and the subsequent current crowding in single finger. As a result, the latch-up of the device takes place. The simulation indicates that the current crowding is formed mainly through an internal path in the silicon. In order to verify the failure mechanism, an improved device with deep-oxide trenches arranged between the adjacent fingers is fabricated. The measured results demonstrate that no failure occurs when the improved device turns off under high-voltage and high-current conditions.

Minna Zhao

Papers

Electrical Characteristic Study of an SOI-LIGBT With Segmented Trenches in the Anode Region

Novel Snapback-Free Reverse-Conducting SOI-LIGBT With Dual Embedded Diodes

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

A U-Shaped Channel SOI-LIGBT With Dual Trenches

Turn-off failure in multi-finger SOI-LIGBT used for single chip inverter ICs