An implantable infusion pump possesses operational functionality that is, at least in part, controlled by software operating in two processor ICs which are configured to perform some different and some duplicate functions. The pump exchanges messages with an external device via telemetry. Each processor controls a different part of the drug infusion mechanism such that both processors must agree on the appropriateness of drug delivery for infusion to occur. Delivery accumulators are incremented and decremented with delivery requests and with deliveries made. When accumulated amounts reach or exceed, quantized deliverable amounts, infusion is made to occur. The accumulators are capable of being incremented by two or more independent types of delivery requests. Operational modes of the infusion device are changed automatically in view of various system errors that are trapped, various system alarm conditions that are detected, and when excess periods of time lapse between pump and external device interactions.

Microprocessor controlled ambulatory medical apparatus with hand held communication device

A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter

An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power and voltages. Passive rectifier circuits are designed in a 0.25 mum CMOS technology using floating gate transistors as rectifying diodes. The 36-stage rectifier can rectify input voltages as low as 50 mV with a voltage gain of 6.4 and operates with received power as low as 5.5 muW(22.6 dBm). Optimized for far field, the circuit operates at a distance of 44 m from a 4 W EIRP source. The high voltage range achieved at low load current make it ideal for use in passively powered sensor networks.

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks

Analysis methods are developed that fully determine a switched-capacitor (SC) dc-dc converter's steady-state performance through evaluation of its output impedance. This analysis method has been verified through simulation and experimentation. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among several switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based dc-dc converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional magnetic-based converter for medium to high conversion ratios.

Analysis and Optimization of Switched-Capacitor DC–DC Converters

A communication device (CD) exchanges messages with an implantable infusion pump via telemetry such that commands are supplied thereto and operational information is obtained therefrom. The CD is controlled, at least in part, by a processor IC according to a software program operating therein and provides feedback to a user via a visual display, an audio alarm, and a vibrational alarm, and allows input from the user via a touch sensitive keypad. Certain input functions are restricted by password. The visual display includes an icon and fixed element display region and a bitmap display region. The fixed element display region includes time and date displays, battery and drug level displays that decrement, and a moving delivery state display. Various screens allow operational or log information to be displayed and/or user entry of commands. Program features when disabled are removed from a series of screen options that can be scrolled through.

Ambulatory medical apparatus with hand held communication device

New MOS charge pumps utilizing the charge transfer switches (CTSs) to direct charge flow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTSs can eliminate the reverse charge sharing phenomenon and further improve the voltage pumping gain. The limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude. Using the new circuit techniques, a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump are demonstrated.

MOS charge pumps for low-voltage operation

The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2- mu m CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate. >

A 100-MHz pipelined CMOS comparator

A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-/spl mu/m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.

https://ir.nctu.edu.tw:443/bitstream/11536/27489/1/000185568500010.pdf

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

An 8-channel 6-bit 16-GS/s time-interleaved analog- to-digital converter (TI ADC) was fabricated using a 65 nm CMOS technology. Each analog-to-digital channel is a 6-bit flash ADC. Its comparators are latches without the preamplifiers. The input-referred offsets of the latches are reduced by digital offset calibration. The TI ADC includes a multi-phase clock generator that uses a delay-locked loop to generate 8 sampling clocks from a reference clock of the same frequency. The uniformity of the sampling intervals is ensured by digital timing-skew calibration. Both the offset calibration and the timing-skew calibration run continuously in the background. At 16 GS/s sampling rate, this ADC chip achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The chip consumes 435 mW from a 1.5 V supply. The ADC active area is 0.93 × 1.58 mm2.

https://ir.nctu.edu.tw:443/bitstream/11536/9084/1/000288762800014.pdf

A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques

This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-/spl mu/m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8/spl times/3.6 mm/sup 2/, and the power consumption is 370 mW with a single 2.5-V supply.

https://ir.nctu.edu.tw:443/bitstream/11536/13754/1/000228773600002.pdf

Jieh-Tsorng Wu

Papers

MOS charge pumps for low-voltage operation

A 100-MHz pipelined CMOS comparator

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration