Electrochemical sensing of biomolecules eliminates the need for the bulky and expensive optical instrumentation required in traditional fluorescence-based sensing assays. Integration of the sensor interface electrodes and active electrochemical detection circuitry on a CMOS substrate miniaturizes the sensing platform, enhancing its portability for use in point-of-care applications, while enabling the high-throughput, highly parallel analysis characteristic of traditional microarrays. This paper describes the design of a four-by-four active sensor array for multiplexed electrochemical biomolecular detection in a standard 0.25-mum CMOS process. Integrated potentiostats, comprised of control amplifiers and dual-slope analog-to-digital converters, stimulate the electrochemical cell and detect the current flowing through the on-chip gold electrodes at each sensor site that results from biomolecular reactions occurring on the chip surface. Post-processing steps needed to fabricate a biologically-compatible surface-electrode array in CMOS that can withstand operation in a harsh electrochemical environment are also described. Experimental results demonstrating the proper operation of the active CMOS array for biomolecular detection include cyclic voltammetry of a reversible redox species, DNA probe density characterization, as well as quantitative and specific DNA hybridization detection.

Active CMOS Sensor Array for Electrochemical Biomolecular Detection

-Electrochemical sensing of biomolecules eliminates the need for the bulky and expensive optical instrumentation required in traditional fluorescence-based sensing assays. Integration of the sensor interface electrodes and active electrochemical detection circuitry on a CMOS substrate miniaturizes the sensing platform, enhancing its portability for use in point-of-care applications, while enabling the high-throughput, highly parallel analysis characteristic of traditional microarrays. This paper describes the design of a four-by-four active sensor array for multiplexed electrochemical biomolecular detection in a standard 0.25-μm CMOS process. Integrated potentiostats, comprised of control amplifiers and dual-slope analog-to-digital converters, stimulate the electrochemical cell and detect the current flowing through the on-chip gold electrodes at each sensor site that results from biomolecular reactions occurring on the chip surface. Post-processing steps needed to fabricate a biologically-compatible surface-electrode array in CMOS that can withstand operation in a harsh electrochemical environment are also described. Experimental results demonstrating the proper operation of the active CMOS array for biomolecular detection include cyclic voltammetry of a reversible redox species, DNA probe density characterization, as well as quantitative and specific DNA hybridization detection.

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

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SOI for digital CMOS VLSI: design considerations and advances

A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Sense-amp based adder with source follower evaluation tree

The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the design methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule.

The circuit and physical design of the POWER4 microprocessor

This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

Jin Ji

Papers

Floating-body effects in partially depleted SOI CMOS circuits