This paper presents a comprehensive study on the influences of parasitic elements on the MOSFET switching performance. A circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances, and reverse current of the freewheeling diode into consideration is given to evaluate the MOSFET switching characteristics. The equations derived for emulating MOSFET switching transients are assessed graphically, which, compared to results obtained merely from simulation or parametric study, can offer better insight into where the changes in switching performance lie when the parasitic elements are varied. The analysis has been successfully substantiated by the experimental results of a 400 V, 6 A test bench. A discussion on the physical meanings behind these parasitic effect phenomena is included. Knowledge about the effects of parasitic elements on the switching behavior serves as an important basis for the design guidelines of fast switching power converters.

Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance

Gallium nitride high electron mobility transistor (GaN HEMT) has matured dramatically over the last few years. A progressively larger number of GaN devices have been manufactured for in field applications ranging from low power voltage regulators to high power infrastructure base-stations. Compared to the state-of-the-art silicon MOSFET, GaN HEMT has a much better figure of merit and shows potential for high-frequency applications. The first generation of 600 V GaN HEMT is intrinsically normally on device. To easily apply normally on GaN HEMT in circuit design, a low-voltage silicon MOSFET is in series to drive the GaN HEMT, which is well known as cascode structure. This paper studies the characteristics and operation principles of a 600 V cascode GaN HEMT. Evaluations of the cascode GaN HEMT performance based on buck converter at hard-switching and soft-switching conditions are presented in detail. Experimental results prove that the cascode GaN HEMT is superior to the silicon MOSFET, but it still needs soft-switching in high-frequency operation due to considerable package and layout parasitic inductors and capacitors. The cascode GaN HEMT is then applied to a 1 MHz 300 W 400 V/12 V LLC converter. A comparison of experimental results with a state-of-the-art silicon MOSFET is provided to validate the advantages of the GaN HEMT.

Evaluation and Application of 600 V GaN HEMT in Cascode Structure

Realistic estimation of power MOSFET switching losses is critical for predicting the maximum junction temperature and efficiency of power electronics circuits. The purpose of this paper is to investigate the internal physics of MOSFET switching processes using a physically based semiconductor device modeling approach, and subsequently examine the commonly used power loss calculation method in light of the new physical insights. The widely accepted output capacitance loss term is found to be redundant and erroneous based on the new modeling and measurement results. In addition, the existing method of approximating switching times with the power MOSFET gate charge parameters grossly overestimates the switching power loss. This paper recommends a new MOSFET gate charge parameter specification and an effective switching time estimation method to compensate for the power loss calculation error introduced by the two-slope voltage transition waveform of the power MOSFET.

New Physical Insights on Power MOSFET Switching Losses

This paper presents the development of a simulation model for high-voltage gallium nitride (GaN) high-electron-mobility transistors (HEMT) in a cascode structure. A method is proposed to accurately extract the device package parasitic inductance, which is of vital importance to better predict the high-frequency switching performance of the device. The simulation model is verified by a double-pulse tester, and the results match well both in terms of device switching waveform and switching energy. Based on the simulation model, an investigation of the package influence on the cascode GaN HEMT is presented, and several critical parasitic inductances are identified and verified. Finally, a detailed loss breakdown is made for a buck converter, including a comparison between hard switching and soft switching. The results indicate that the switching loss is a dominant part of the total loss under hard-switching conditions in megahertz high-frequency range and below 8~10 A operation current; therefore, soft switching is preferred to achieve high-frequency and high-efficiency operation of the high-voltage GaN HEMT.

Package Parasitic Inductance Extraction and Simulation Model Development for the High-Voltage Cascode GaN HEMT

This paper presents an accurate analytical model to calculate the power loss of a high voltage Gallium Nitride high electron mobility transistor (GaN HEMT) in cascode configuration. The proposed model considers the package and PCB parasitic inductances, the nonlinearity of the junction capacitors, and the transconductance of the cascode GaN transistor. The switching process is illustrated in detail, including the interaction of the low voltage Si MOSFET and the high voltage GaN HEMT in cascode configuration. The switching loss is obtained by solving the equivalent circuits during the switching transition. The analytical results show that the turn-on loss dominates in hard-switching conditions while the turn-off loss is negligible, due to the intrinsic current source driving mechanism. The accuracy of the proposed model is validated by numerous experimental results. The results of both the analytical model and experiments suggest that soft-switching is critical for high voltage GaN in high-frequency high-efficiency applications.

Analytical Loss Model of High Voltage GaN HEMT in Cascode Configuration

An accurate analytical model is proposed in this paper to calculate the power loss of a metal-oxide semiconductor field-effect transistor. The nonlinearity of the capacitors of the devices and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc., are considered in the model. In addition, the ringing is always observed in the switching power supply, which is ignored in the traditional loss model. In this paper, the ringing loss is analyzed in a simple way with a clear physical meaning. Based on this model, the circuit power loss could be accurately predicted. Experimental results are provided to verify the model. The simulation results match the experimental results very well, even at 2-MHz switching frequency.

Analytical loss model of power MOSFET

This paper proposes a general design guideline for the voltage regulator (VR) to achieve adaptive voltage position (AVP). All existing control methods are covered for different kinds of output filter capacitors. Based on the small-signal model analysis, the output impedance and system control bandwidth are discussed. Following the proposed design guidelines, simulation and experimental results demonstrate very good VR transient response.

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Adaptive voltage position design for voltage regulators

In this paper, a self-driven zero-voltage-switching (ZVS) full-bridge converter is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and Self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary side synchronous rectifier (SR) as the snubber capacitor of the primary side switches. Compared with the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared with the existed level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal is very clean and suitable for high-frequency applications. A 1-MHz, 1.2-V/70-A prototype is built to verify the analysis. Experimental results show that it can achieve 81.7% efficiency. And there is an efficiency improvement of 4.7% over conventional phase-shifted full-bridge converter with an external driver.

1-MHz self-driven ZVS full-bridge converter for 48-V power pod and DC/DC brick

In conventional high frequency 12-V input voltage regulators (VR), large gate driver loss and body diode conduction loss raise crucial challenges to its gate driver implementation. The proposed self-driven topologies are basically buck-derived multiphase interleaving soft switching topologies, which eliminate the synchronous rectifier MOSFET drivers and save driving loss and body diode loss, so that it is a high efficiency, high power density solution for future microprocessors. A 1U four-phase 1.3-V/100-A VRM running at 1MHz demonstrates its advantages (cost, size and efficiency) over the conventional multiphase buck converter.

A self-driven soft-switching voltage regulator for future microprocessors

Today's voltage regulator (VR) for the microprocessor requires a current loop to achieve adaptive voltage positioning and phase current sharing. A fundamental limitation, current loop sample hold effect, limits the control bandwidth to be pushed beyond 1/6 of the switching frequency. This paper reveals the limitation of the control bandwidth of a two-phase buck converter using peak current control scheme. The limitation can be overcome by coupling the two output inductors. A new small signal model is proposed to study the sample hold effect in coupled-inductor implementations. The relationship between the coupling coefficient and the sample hold effect is then discussed. Based on these understandings, a strongly coupled two-phase buck converter has double the bandwidth of the noncoupled VR; and this is experimentally verified

Jinghai Zhou

Papers

Analytical loss model of power MOSFET

Adaptive voltage position design for voltage regulators

1-MHz self-driven ZVS full-bridge converter for 48-V power pod and DC/DC brick

A self-driven soft-switching voltage regulator for future microprocessors

Small Signal Modeling of a High Bandwidth Voltage Regulator Using Coupled Inductors