An all-polymer semiconductor integrated device is demonstrated with a high-mobility conjugated polymer field-effect transistor (FET) driving a polymer light-emitting diode (LED) of similar size. The FET uses regioregular poly(hexylthiophene). Its performance approaches that of inorganic amorphous silicon FETs, with field-effect mobilities of 0.05 to 0.1 square centimeters per volt second and ON-OFF current ratios of >10 6 . The high mobility is attributed to the formation of extended polaron states as a result of local self-organization, in contrast to the variable-range hopping of self-localized polarons found in more disordered polymers. The FET-LED device represents a step toward all-polymer optoelectronic integrated circuits such as active-matrix polymer LED displays.

https://science.sciencemag.org/content/sci/280/5370/1741.full.pdf

Integrated Optoelectronic Devices Based on Conjugated Polymers

Organic-inorganic hybrid materials promise both the superior carrier mobility of inorganic semiconductors and the processability of organic materials A thin-film field-effect transistor having an organic-inorganic hybrid material as the semiconducting channel was demonstrated Hybrids based on the perovskite structure crystallize from solution to form oriented molecular-scale composites of alternating organic and inorganic sheets Spin-coated thin films of the semiconducting perovskite (C(6)H(5)C(2)H(4)NH(3))(2)SnI(4) form the conducting channel, with field-effect mobilities of 06 square centimeters per volt-second and current modulation greater than 10(4) Molecular engineering of the organic and inorganic components of the hybrids is expected to further improve device performance for low-cost thin-film transistors

https://science.sciencemag.org/content/sci/286/5441/945.full.pdf

Organic-inorganic hybrid materials as semiconducting channels in thin-film field-effect transistors

The thiophene oligomer α-hexathienylene (α-6T) has been successfully used as the active semiconducting material in thin-film transistors. Field-induced conductivity in thin-film transistors with α-6T active layers occurs only near the interfacial plane, whereas the residual conductivity caused by unintentional doping scales with the thickness of the layer. The two-dimensional nature of the field-induced conductivity is due not to any anisotropy in transport with respect to any molecular axis but to interface effects. Optimized methods of device fabrication have resulted in high field-effect mobilities and on/off current ratios of > 106. The current densities and switching speeds are good enough to allow consideration of these devices in practical large-area electronic circuits.

https://science.sciencemag.org/content/sci/268/5208/270.full.pdf

Organic transistors: two-dimensional transport and improved electrical characteristics.

Yu Bai,†,‡ Ivań Mora-Sero,́ Filippo De Angelis, Juan Bisquert, and Peng Wang*,† †State Key Laboratory of Polymer Physics and Chemistry, Changchun Institute of Applied Chemistry, Chinese Academy of Sciences, Changchun 130022, China ‡Institute of Chemistry and Energy Material Innovation, Academy of Fundamental Interdisciplinary Sciences, Harbin Institute of Technology, Harbin 150080, China Photovoltaic and Optoelectronic Devices Group, Departament de Física, Universitat Jaume I, 12071 Castello,́ Spain Istituto CNR di Scienze e Tecnologie Molecolari, c/o Dipartimento di Chimica, Universita ̀ di Perugia, via Elce di Sotto 8, I-06123 Perugia, Italy

Titanium Dioxide Nanomaterials for Photovoltaic Applications

Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it has the disadvantages of poor resolution, large overlap capacitances, and film thickness limitations, resulting in slow circuit speeds and high operating voltages. Here, we demonstrate a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100–400 nm. The use of a crosslinkable polymer gate dielectric with 30–50 nm thickness ensures that basic scaling requirements are fulfilled and that operating voltages are below 5 V. The device architecture minimizes contact resistance effects, enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes parasitic overlap capacitance to values as low as 0.2–0.6 pF mm−1, and allows transition frequencies of fT = 1.6 MHz to be reached. Our self-aligned process provides a way to improve the performance of printed organic transistor circuits by downscaling, while remaining compatible with the requirements of large-area, flexible electronics manufacturing.

Downscaling of self-aligned, all-printed polymer thin-film transistors

We present a new theory describing current‐voltage characteristics of amorphous silicon thin‐film transistors. We calculate the output conductance in saturation by considering channel shortening effects caused by the space‐charge‐limited current in the pinch‐off region. In this model the drain current is expressed through the free‐carrier concentration at the source side of the channel. This allows us to obtain an accurate description of the different operating regimes of a thin‐film transistor using one equation that accounts for the dependence of the free‐carrier concentration in the channel for different regimes. Our model is in good agreement both with experimental data and the results of our two‐dimensional computer simulation. This approach allows one to account for different distributions of localized states in the energy gap. The model has also been developed to be incorporated into a circuit simulator and used for computer‐aided design of amorphous silicon integrated circuits.

A new analytic model for amorphous silicon thin‐film transistors

We present a simple analytic model for calculating the trapped‐charge density as a function of free‐carrier concentration for realistic density‐of‐states distributions in hydrogenated amorphous silicon. This is necessary to understand the behavior of amorphous silicon devices as their characteristics are largely determined by the high concentration of charge trapped by the localized stages in the band gap. Such a model is useful as an aid in exploring the nature of the charge‐trapping process and for the efficient numerical simulation of amorphous‐silicon devices such as thin‐film transistors.

An analytic model for calculating trapped charge in amorphous silicon

A semianalytic theory to describe both the current-voltage and capacitance-voltage characteristics of amorphous silicon thin-film transistors on the basis of their physics of operation is presented. In this model, the drain current is directly related to the electron concentration at the source side of the channel. This enables one to describe the various regimes of operation of these devices (i.e. subthreshold or above threshold) using only one equation. The output conductance of these devices in saturation is also considered, and it is shown that the finite output impedance is a consequence of the drain voltage modulating the effective channel length by creating a space-charge limited current region of variable length near the drain. The results of this model are in good agreement both with experimental data and the results of comprehensive two-dimensional simulations. These device models have been successfully incorporated into a SPICE circuit simulation program. >

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

Through the use of two‐dimensional computer simulations, we study short‐channel and overlap effects in amorphous silicon thin‐film transistors. As large‐area fabrication techniques can lead to conductive source‐drain overlaps being deposited on a portion of the upper passivation layer of inverted‐gate thin‐film transistors, it is important to understand how these overlaps affect performance. In saturation, charge accumulates under the drain overlap shortening the effective channel length. We contrast the performance of thin‐film transistors with and without overlaps as a function of gate length.

Simulations of short‐channel and overlap effects in amorphous silicon thin‐film transistors

We present the results of experimental and theoretical studies of capacitance‐voltage characteristics of amorphous silicon thin‐film transistors. The small‐signal capacitances are calculated as derivatives of channel charge with respect to terminal voltages. The induced charge is evaluated using the same charge‐control model for an amorphous silicon thin‐film transistor as we used to calculate the current‐voltage characteristics of this device. The calculated dependences of capacitances on bias voltages are in good agreement with our experimental data. The capacitance‐voltage model is suitable for incorporation into a circuit simulator and can be used for computer‐aided design of a‐Si integrated circuits.

John G. Shaw

Papers

A new analytic model for amorphous silicon thin‐film transistors

An analytic model for calculating trapped charge in amorphous silicon

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

Simulations of short‐channel and overlap effects in amorphous silicon thin‐film transistors

Capacitance‐voltage characteristics of amorphous silicon thin‐film transistors