An exemplary NAND string memory array provides for capacitive boosting of a half-selected memory cell channel to reduce program disturb effects of the half selected cell. To reduce the effect of leakage current degradation of the boosted level, multiple programming pulses of a shorter duration are employed to limit the time period during which such leakage currents may degrade the voltage within the unselected NAND strings. In addition, multiple series select devices at one or both ends of each NAND string further ensure reduced leakage through such select devices, for both unselected and selected NAND strings. In certain exemplary embodiments, a memory array includes series-connected NAND strings of memory cell transistors having a charge storage dielectric, and includes more than one plane of memory cells formed above a substrate.

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed through non-selected memory cells. Each NAND string includes two block select devices for respectively coupling one end of the NAND string to a global bit line, and the other end to a shared bias node. Pairs of NAND strings within a block share the same global bit line. The memory cells are preferably depletion mode SONOS devices, as are the block select devices. The memory cells may be programmed to a near depletion threshold voltage, and the block select devices are maintained in a programmed state having a near depletion mode threshold voltage. NAND strings on more than one layer may be connected to global bit lines on a single layer. By interleaving the NAND strings on each memory level and using two shared bias nodes per block, very little additional overhead is required for the switch devices at each end of the NAND strings. The NAND strings on different memory levels are preferably connected together by way of vertical stacked vias, each preferably connecting to more than one memory level. Each memory level may be produced with less than three masks per level.

Method for fabricating programmable memory array structures incorporating series-connected transistor strings

An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

Memory array incorporating memory cells arranged in NAND strings

NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same

Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Experimental data showing the degradation in performance of polysilicon thin-film transistors (TFTs) under a variety of bias stress conditions are presented. A model is proposed to explain these effects whereby device performance degrades due to changes in the effective density of defect states in the material. Unlike single-crystal devices which degrade from hot-carrier effects, poly-Si TFTs are believed to degrade primarily due to the presence of high carrier densities in the channel. Good agreement between computer simulations of the device characteristics and experimental data ia demonstrated. It is shown that stressing under transient conditions leads to a more severe performance degradation than stressing under comparable steady-state conditions. >

Physical models for degradation effects in polysilicon thin-film transistors

A semianalytic theory to describe both the current-voltage and capacitance-voltage characteristics of amorphous silicon thin-film transistors on the basis of their physics of operation is presented. In this model, the drain current is directly related to the electron concentration at the source side of the channel. This enables one to describe the various regimes of operation of these devices (i.e. subthreshold or above threshold) using only one equation. The output conductance of these devices in saturation is also considered, and it is shown that the finite output impedance is a consequence of the drain voltage modulating the effective channel length by creating a space-charge limited current region of variable length near the drain. The results of this model are in good agreement both with experimental data and the results of comprehensive two-dimensional simulations. These device models have been successfully incorporated into a SPICE circuit simulation program. >

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

High-voltage MOSFETs have been fabricated in a large-area thin-film amorphous silicon technology. The transistors have an offset gate structure which allows them to operate at an excess of 400 V. Basic fabrication steps and structure are discussed. These transistors have a gate-controlled region in series with an offset region where the current is space charge limited. The I/sub D/-V/sub D/ characteristics exhibit a unique instability under drain voltage stress; there is a parallel shift in the I/sub D/ versus V/sub D/ characteristic to a higher V/sub D/. This instability arises from the creation of localized states in the a-Si during depletion. It is analyzed through experiment and two-dimensional simulation. Structural variations are described, including the application of a field plate, to stabilize transistor drive current. Reliability and process uniformity are discussed for arrays of transistors. An appropriate circuit simulation model is discussed. Operation of output drive circuits with high-voltage thin-film transistors (TFTs) is shown, and the application of these to an electrographic plotter is described. >

High-voltage amorphous silicon thin-film transistors

The leakage current of an arbitrary number of series-connected polysilicon Thin Film Transistors (TFTs) with a common gate is shown to be easily computed from the I-V characteristics of a single FET for the first time, both by an analytical model and by graphical techniques. Good agreement with experimental data is obtained for drain biases greater than /spl sim/1 V. The work is also applicable to single crystal Silicon-On-Insulator (SOI) TFTs. >

Leakage current modeling of series-connected thin film transistors

In this paper we show good agreement between numerical simulations and experimental data of the electrical characteristics of multiple gate poly-crystalline silicon (poly-Si) thin film transistors (TFTs). We focus on leakage current, as this is the most critical TFT characteristic for pixel switches in high resolution active matrix liquid crystal displays (AMLCD). The minimum leakage current ( Imin) determines grey level performance, while the sharpness of the minimum determines the range of negative gate bias required to maintain leakages close to I m i n , Leakage currents in poly-Si TFTs have been shown to be caused by a high electric field tunneling mechanism at specific traps, probably associated with intra-grain defects [l]. Various strategies are currently being employed to reduce leakage currents, but multiple gate devices [2] are preferential on account of their ease of implementation. In multiple gate structures the gated regions are connected by heavily doped channel regions. Experimentally we show [3] that while NMOS multiple gate structures reduce I m i n , they do not reduce the slope of the leakage current increase with larger reverse gate biases, V, , . This result is contrary to initial expectations that multiple gate TFTs would reduce the slope of the reverse V, , leakage, as the drain bias (Vds) is divided between the gated regions, and as minority carriers generated in the drain high field region would recombine in the (or one of the) heavily doped channel region(s) without reaching the source. In this paper we demonstrate, for the first time, why multiple gate TFTs have the same leakage increase a t negative gate voltages as single gate TFTs. Leakage currents are simulated by adding a single tunneling trap with a temperature independent tunneling mechanism to an effective medium model [l]. With increasing reverse V, , the maximum channel electric field moves from the edge of the gated region (second) near the TFT drain to the drain edge of the gated region nearest to the source (first), causing the leakage current slope to be independent of the number of gates. Multiple gate structures lower Imin as the vds is divided between the different gated regions, reducing the peak channel electric field. The leakage of a double gate TFT a t Vds = 10 Volts is higher than that of a single gate device a t vds=Sv. The experimental data of the dependence of leakage on reverse V,, are in good agreement with the simulation results. Contour plots of the channel electric field for vds= 1OV in a double gate TFT show that for VgS above the value needed for minimum leakage current (Vgsmin) the highest field is near to the edge of the gated region nearest the device drain. Carrier concentration profiles show that few minority carriers generated in the high field region flow through the central heavily doped region to the source. For V, , more negative than Vgsmin the point of highest electric field moves to the drain edge of the gated region nearest to the source, Once the gated region nearest the drain becomes sufficiently conductive, the largest potential drop within the TFT is a t the drain end of the source gated region. Now minority carriers generated by a tunneling mechanism in this first gated region flow to the source, increasing the leakage current. This causes double gate TFTs to have the same slope reverse gate bias characteristics as single gate TFTs. TFTs with progressively higher number of gates also have the same leakage slope as a single gate device as the point of highest channel electric field always moves to the drain edge of the gated region nearest to the source.

M. Hack

Papers

Physical models for degradation effects in polysilicon thin-film transistors

Physical models for amorphous-silicon thin-film transistors and their implementation in a circuit simulation program

High-voltage amorphous silicon thin-film transistors

Leakage current modeling of series-connected thin film transistors

Analysis of leakage currents in multiple gate poly-si thin film transistors for active matrix liquid crystal displays