Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 1990s, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance significantly better than that achievable with conformal step coverage. This attribute of superconformal deposition, which we call superfilling, and its relation to plating additives are discussed, and we present a numerical model that represents the shape-change behavior of this system.

Damascene Copper electroplating for chip interconnections

Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

The design and fabrication of three-dimensional multifunctional architectures from the appropriate nanoscale building blocks, including the strategic use of void space and deliberate disorder as design components, permits a re-examination of devices that produce or store energy as discussed in this critical review. The appropriate electronic, ionic, and electrochemical requirements for such devices may now be assembled into nanoarchitectures on the bench-top through the synthesis of low density, ultraporous nanoarchitectures that meld high surface area for heterogeneous reactions with a continuous, porous network for rapid molecular flux. Such nanoarchitectures amplify the nature of electrified interfaces and challenge the standard ways in which electrochemically active materials are both understood and used for energy storage. An architectural viewpoint provides a powerful metaphor to guide chemists and materials scientists in the design of energy-storing nanoarchitectures that depart from the hegemony of periodicity and order with the promise—and demonstration—of even higher performance (265 references).

Multifunctional 3D nanoarchitectures for energy storage and conversion.

Atomic layer deposition (ALD) has been studied for several decades now, but the interest in ALD of metal and nitride thin films has increased only recently, driven by the need for highly conformal nanoscale thin films in modern semiconductor device manufacturing technology. ALD is a very promising deposition technique with the ability to produce thin films with excellent conformality and compositional control with atomic scale dimensions. However, the applications of metals and nitrides ALD in semiconductor device processes require a deeper understanding about the underlying deposition process as well as the physical and electrical properties of the deposited films. This article reviews the current research efforts in ALD for metal and nitride films as well as their applications in modern semiconductor device fabrication.

Atomic layer deposition of metal and nitride thin films: Current research efforts and applications for semiconductor device processing

An apparatus and method for an electrodeposition or electroetching system. A thin metal film is deposited or etched by electrical current through an electrolytic bath flowing toward and in contact with a target on which the film is disposed. Uniformity of deposition or etching is promoted, particularly at the edge of the target film, by baffle and shield members through which the bath passes as it flows toward the target. The baffle has a plurality of openings disposed to control the localized current flow across the cross section of the workpiece/wafer. Disposed near the edge of the target, the shield member shapes the potential field and the current line so that it is uniform.

Method and apparatus for enhancing the uniformity of electrodeposition or electroetching

An apparatus and method for an electrodeposition or electroetching system. A thin metal film is deposited or etched by electrical current through an electrolytic bath flowing toward and in contact with a target on which the film is disposed. Uniformity of deposition or etching is promoted, particularly at the edge of the target film, by, baffle and shield members through which the bath passes as it flows toward the target. The baffle has a plurality of openings disposed to control the localized current flow across the cross section of the workpiece/wafer. Disposed near the edge of the target, the shield member shapes the potential field and the current line so that it is uniform.

Method for enhancing the uniformity of electrodeposition or electroetching

An anode assembly including a perforated anode. A perforated anode holder holds the anode. The anode holder includes perforations at least in a bottom wall such that plating solution may flow through perforations in the anode holder and perforations in the anode. An anode isolator separates the anode and a cathode. The anode isolator includes at least one curvilinear surface.

Anode design for semiconductor deposition

Current Distribution and Shape Change in Electrodeposition of Thin Films for Microelectronic Fabrication

Recently, IBM announced the implementation of a full copper interconnect scheme which will be manufactured on its high-performance 0.20 /spl mu/m CMOS products later this year. Features of this technology are presented here, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data is presented from this testing, ranging from experiments designed to promote copper contamination of the MOS devices, to functional stressing of packaged SRAM modules. A fully-functional high-performance microprocessor with 6 levels of Cu wiring has also been demonstrated. The results in all areas are equal to or better than standards set by our current Al(Cu) wiring technology. This work demonstrates that the potential problems associated with copper wiring can be overcome to produce reliable and properly-functioning ULSI CMOS chips with a cost-effective, extendible process.

John Owen Dukovic

Papers

Method and apparatus for enhancing the uniformity of electrodeposition or electroetching

Method for enhancing the uniformity of electrodeposition or electroetching

Anode design for semiconductor deposition

Current Distribution and Shape Change in Electrodeposition of Thin Films for Microelectronic Fabrication

Copper dual damascene wiring for sub-0.25 /spl mu/m CMOS technology