R
Ronald D. Goldblatt
Researcher at IBM
Publications - 34
Citations - 1063
Ronald D. Goldblatt is an academic researcher from IBM. The author has contributed to research in topics: Copper interconnect & Layer (electronics). The author has an hindex of 14, co-authored 34 publications receiving 1056 citations.
Papers
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Proceedings ArticleDOI
Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology
Daniel C. Edelstein,John E. Heidenreich,Ronald D. Goldblatt,William J. Cote,Cyprian E. Uzoh,Naftali E. Lustig,Peter Roper,Thomas L. McDevitt,W. Motsiff,A. Simon,J. Dukovic,Richard A. Wachnik,H. Rathore,R. Schulz,L. Su,Stephen E. Luce,J. Slattery +16 more
TL;DR: In this paper, the first fully integrated ULSI CMOS/copper interconnect technology is presented, where up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a poly-contacting pitch of 1.81 /spl µ/m.
Patent
Lamination method for coating the sidewall or filling a cavity in a substrate
TL;DR: In this article, the material is disposed on the surface of the substrate and pressure is applied causing the material to flow, first coating the sidewall of the hole and on the continued application of pressure the material flows to completely fill the hole.
Journal ArticleDOI
A 480 MHz RISC microprocessor in a 0.12 /spl mu/m L/sub eff/ CMOS technology with copper interconnects
Chekib Akrout,J. Bialas,M. Canada,D. Cawthron,J. Corr,Bijan Davari,R. Floyd,Stephen Frank Geissler,Ronald D. Goldblatt,Robert M. Houle,Paul D. Kartschoke,David Kramer,P. McCormick,Norman J. Rohrer,Gerard M. Salem,R. Schulz,L. Su,L. Whitney +17 more
TL;DR: In this article, a 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors.
Proceedings ArticleDOI
A high performance 0.13 /spl mu/m copper BEOL technology with low-k dielectric
Ronald D. Goldblatt,Birendra N. Agarwala,M.B. Anand,Edward Barth,G. A. Biery,Z.G. Chen,Stephan A. Cohen,J.B. Connolly,Andy Cowley,Timothy J. Dalton,S Das,Charles R. Davis,Alina Deutsch,C. DeWan,Daniel C. Edelstein,P.A. Emmi,C.G. Faltermeier,John A. Fitzsimmons,J. L. Hedrick,John E. Heidenreich,Chenming Hu,J.P. Hummel,P. Jones,Erdem Kaltalioglu,B.E. Kastenmeier,Mahadevaiyer Krishnan,William F. Landers,Eric G. Liniger,Junjun Liu,Naftali E. Lustig,Sandra G. Malhotra,D.K. Manger,Vincent J. McGahay,R. Mih,Henry A. Nye,Sampath Purushothaman,H. Rathore,Soon-Cheon Seo,Timothy M. Shaw,Andrew H. Simon,Spooner Terry A,M. Stetter,Richard A. Wachnik,J.G. Ryan +43 more
TL;DR: In this paper, the integration of dual damascene copper with low-k dielectric at the 0.13 /spl mu/m technology node is described, and the integration is achieved while maintaining reliability standards.
Proceedings ArticleDOI
A high performance 90nm SOI technology with 0.992 /spl mu/m 2 6T-SRAM cell
Mukesh Khare,S.H. Ku,Ricardo A. Donaton,Stephen E. Greco,Colin J. Brodsky,X. Chen,Anthony I. Chou,Ronald A. DellaGuardia,Sadanand V. Deshpande,Bruce B. Doris,S.K.H. Fung,Allen H. Gabor,Michael A. Gribelyuk,Steven J. Holmes,F. Jamin,W. Lai,Woo-Hyeong Lee,Yujun Li,P.A. McFarland,Renee T. Mo,Steven W. Mittl,Shreesh Narasimha,D. Nielsen,Robert J. Purtell,Werner A. Rausch,Sujatha Sankaran,J. Snare,Len Y. Tsou,A. Vayshenker,Tina Wagner,D. Wehella-Gamage,Ernest Y. Wu,S. Wu,W. Yan,E. Barth,Richard A. Ferguson,Percy V. Gilbert,Dominic J. Schepis,Akihisa Sekiguchi,Ronald D. Goldblatt,Jeffrey J. Welser,Karl Paul Muller,Paul D. Agnello +42 more
TL;DR: In this paper, the smallest 6T SRAM cell reported to date with a cell area of 0.992 /spl mu/m/sup 2 was presented, which utilizes SiLK/spl trade/low-K dielectric material with a multilayer hard mask stack.